ELE 405 Digital Computer Design

 Fall 1997 Handouts

 Spring 1999 Handouts and Other Info

 

Announcements - May 9, 1999:

• Practice Final Exam now available;
• and once you've done it, Solutions to Practice Final Exam are also available.

 

Catalog Description.

ELE 405 Digital Computer Design (I and II, 4) Hardware implementation of digital computers. Arithmetic circuits, memory interface, data path, control path, input/output. Synthesis tools. Gate level design, simulation, construction and verification of a simple digital computer. (Lec. 3, Lab. 3) Pre: ELE 305. Staff

Additional Information

1. Rationale. The main goal is to gain experience in complex digital system design. This is achieved via the simulation and construction of the hardware of an operational digital computer.

 

 
 
 
 
 

This course is a key component of the new computer engineering curriculum. The design component of this course is also key, forming one of the major steps in the major's Integrated Computer Engineering Design (ICED) Curriculum integrated multi-year design project. The project entails the design, simulation, construction, and debugging of the hardware and software of an operational digital computer, with compiler, and the interconnection of the students' computers into a network.
 

2. Place in Curriculum. This course is required for the computer engineering major. It is an elective for the electrical engineering major.

Course Outline - typical semester; see syllabus for current content

1. General digital system design
1. Setting design goals
2. Algorithmic state machines and other design tools
3. Synchronous digital systems - design and use of the clock
4. Data path function
5. Control path function
2. Data path design
1. MUX's
2. Buses
3. Simplicity and generality of design
4. Adders and ALU's
5. Synthesis tools
6. Low-power considerations
3. Control path implementation
1. One-hot method
2. Encoded states
3. Microprogramming
4. Synthesis tools
4. Advanced logic design
1. Flip-flop design
2. Input/Output
3. Loading
4. Transmission line effects
5. Introduction to fault tolerance
6. Asynchronous circuit design - classical
7. Asynchronous circuit design - modern
5. Memory
1. Dynamic RAM usage
2. Paging modes
3. Cache implementation
6. Verification
1. Testing strategies
2. Benchmarks

Fall 1997 Course Handouts

Partial listing. Postscript files.

Syllabus.

Projects:

• Project 1. - Introduction to ELE Environment and Mentor Graphics CAD tools.
• Project 2. - ALU Design.
• Term Project Overview. - Design of "RHODY" Digital Computer; architectural specification.
• Project 3. - Term Project: Set-up; ASM and high-level data path.
• Project 4. - Term Project: Detailed Data Path.
• Project 5. - Term Project: Control Path.
• Project 6. - Term Project: System Integration; addition of memory, overall test and performance evaluation.

Useful Links

• Motorola FAST and LS TTL Data Book Online.

 

Spring 1999 Course Handouts and Other Info

Syllabus - postscript file, small
A Brief Guide to Report Writing - ~50KB postscript - relevant for most labs.
Practice Midterm - html
Transmission Line Spreadsheet - MS Excel 97, ~67KB
Canned CPU Design- html
Practice Final Exam - html
Practice Final Exam Solutions - html

Labs:

• Lab1. - Introduction to the ICED Sun Hardware. - postscript file, big (~12 MBytes)
• Note1: The tutorial in this Lab was written primarily with former ELE 305 students in mind. Others should consult the tutorials on the ELE 305 home page first or concurrently, especially Tutorials 1-3. Look at Tutorial 4 when you're ready to do structural simulation (back annotation).

Note2: ELE 305ers will find much of this document to be review, but there is still a lot of new and important stuff to read about.
 
Note3: See: A Brief Guide to Report Writing - ~50KB postscript - relevant for second part of Lab1.
• Lab 2. - Interfacing to the FPGA and your Computers - html
• Lab 3. - ICED Computer-to-Host Interface - html
• Lab 4. - ICED System Integration and Test - html