Verification of ILP Speedups in the 10's 
for Disjoint Eager Execution

Augustus K. Uht
Department of Electrical and Computer Engineering
Kelley Hall
Univ. of Rhode Island
Kingston, RI 02881, USA
email: uht@ele.uri.edu
 
 

Technical Report No. 0697-0001, Dept. of Electrical and Computer Engineering, University of Rhode Island, Kingston, RI 02881-0805, USA

Submitted to: The 30th International Symposium on Microarchitecture (MICRO-30).

Abstract

Disjoint Eager Execution (DEE) has demonstrated Instruction Level Parallelism (ILP) speedups of a factor of 30 in simulations. Theoretical and practical arguments verifying these gains are presented. This includes the use of Amdahl's Law, analysis of the partial trace of a detailed simulation of a SPECint92 benchmark, and analysis of the effect on cycle time of the scheduling hardware of the proposed Levo DEE-realization prototype. The static tree heuristic used to economically realize DEE in Levo is also examined. In particular, the shape of the tree is verified via formal proofs, and the variations in the dimensions of the tree with respect to available resources and branch predictor accuracy are modeled and studied.