Happy Holidays!
Welcome to IEEE TCCA Email-Monthly, Dec. 2004:
*30th August - 2nd September, 2005 in Lisboa, Portugal *Submission Deadline: 31th January, 2005 *Submitted by: Kevin Skadron <skadron@cs.virginia.edu>
COMPUTER ARCHITECTURE *February 12-16, 2005, Palace Hotel, San Francisco, CA *Submitted by: Christoforos Kozyrakis <christos@minos.stanford.edu>
*June 27-30, 2005, Monte Carlo Resort, Las Vegas, Nevada, USA *SUBMISSION DEADLINE: Feb. 7, 2005 *Submitted by: "Toomas P. Plaks" <plakst@lsbu.ac.uk> *CALL FOR PAPERS http://www.scism.lsbu.ac.uk/ERA/ersa.html
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qyang@ele.uri.edu * To subscribe to this mailing list, please sign up at <http://www.computer.org/TCsignup/index.htm>
~~~~~~~~~~~~~~~~~~~~~~~~~~~~Message Details~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ======================== (workshop INTERACT-9 call-for-papers)========
Call for Papers of
Topic 7: Parallel Computer Architecture and ILP
of the Euro-Par 2005 Conference
30th August - 2nd September, 2005 in Lisboa, Portugal
http://europar05.di.fct.unl.pt/
Keydates:
Submission Deadline: 31th January, 2005 Author Notification: 3rd May, 2005 Camera Ready papers due: 30th May, 2005
Instruction-Level Parallelism and parallel processing techniques are present in most contemporary computing systems. The scope of this topic includes (but is not limited to) parallel computer architectures, processor architecture (architecture and microarchitecture as well as compilation), the impact of emerging microprocessor architectures on parallel computer architectures, innovative memory designs to hide and reduce the access latency, multi-threading, and the impact of emerging applications on parallel computer architecture design. Our aim is to bring together researchers in the fields of parallel computer architecture and processor architecture. We invite researchers with interest in both conventional and non-conventional approaches to
participate. Papers are being sought on all aspects of parallel computer architecture, processor architecture and microarchitecture, including (but not limited to) the following list of topics.
Topic Committee:
Global Chair: Theo Ungerer, University of Augsburg, Germany Local Chair : Pedro Trancoso, University of Cyprus, Cyprus Vice-Chair : Josep-Lluis Larriba-Pey, UPC-Barcelona, Spain Vice-Chair : Kevin Skadron, University of Virginia, USA
COMPUTER ARCHITECTURE (HPCA-11)
ADVANCE PROGRAM
February 12-16, 2005
Palace Hotel, San Francisco, CA
http://www.hpcaconf.org/hpca11
Saturday February 12, 2005
8:30-5:00 All Day Events
Tutorial T2: All You Want To Know About Circuits As An Architect But Were Afraid To Ask
Shih-Lien Lu, MRL/MTL Intel
Steven Hsu, CRL/MTL Intel
Workshop W1: CAECW-8: Computer Architecture Evaluation using Commercial Workloads
Kimberly Keeton, HP Labs
Lieven Eeckhout, Ghent University
Pankaj Mehra, HP
Ravi Iyer, Intel Labs
Russell Clapp, Fabric7 Systems, Inc.
Workshop W2: HPCRI: High Performance Computing Reliability Issues
Padma Apparao, Intel Labs
Greg Averill, Intel Labs
1:00-5:00 Afternoon Events
Tutorial T1: A Practical Approach To Performance Analysis And Modeling Of Large-Scale Systems
Adolfy Hoisie, Los Alamos National Laboratory
Darren Kerbyson, Los Alamos National Laboratory
Sunday February 13, 2005
8:30-12:00 Morning Events
Tutorial T3: Volatile Memory Performance Comparison
J. Thomas Pawlowski, Micron Technology, Inc.
8:30-5:00 All Day Events
Workshop W4: INTERACT-9: Interaction between Compilers and Computer Architectures
Gyungho Lee, University of Illinois at Chicago
Wei-Chung Hsu, University of Minnesota
Workshop W5: PPHEC-2: Productivity and Performance in High-End Computing
Ram Rajamony, IBM
Workshop W6: Hardware Performance Monitor Design and Functionality
Olaf Lubeck, Los Alamos National Laboratory
Phil Mucci, University of Tennessee
Mike Lang, Los Alamos National Laboratory
Rob Fowler, Rice University
1:00-5:00 Afternoon Events
Workshop W3: Architecture Research using FPGA Platforms
Arvind, MIT
Krste Asanovic, MIT
Derek Chiou, UT Austin
James Hoe, CMU
Christoforos Kozyrakis, Stanford
Shih-Lien Lu, Intel
6:30-8:00 Reception at the hotel
Monday February 14, 2005
8:15-8:30 Welcome
8:30-9:30 Keynote Speech: "Trends in High-Performance Processors"
Fred Weber, Chief Technology Officer, AMD
Chair: Josep Torrellas
9:30-10:00 Break
10:00-12:00 SESSION 1: PROCESSOR ARCHITECTURE
Chair: Antonio Gonzalez, Universitat Politecnica de Catalunya and Intel Labs
Multithreaded Value Prediction
Nathan Tuck, University of California, San Diego
Dean M. Tullsen, University of California, San Diego
Checkpointed Early Load Retirement
Nevin Kirman, Cornell University
Meyrem Kirman, Cornell University
Mainak Chaudhuri, Cornell University
Jose F. Martinez, Cornell University
Microarchitectural Wire Management for Performance and Power in
Partitioned Architectures
Rajeev Balasubramonian, University of Utah
Naveen Muralimanohar, University of Utah
Karthik Ramani, University of Utah
Venkatanand Venkatachalapathy, University of Utah
A Small, Fast and Low-Power Register File by Bit-Partitioning
Masaaki Kondo, University of Tokyo
Hiroshi Nakamura, University of Tokyo
12:00-1:30 Intel-sponsored lunch
1:30-3:30 SESSION 2: TEMPERATURE, ENERGY, AND POWER
Chair: Krste Asanovic, MIT
Accurate Energy Dissipation and Thermal Modeling for Nanometer-Scale
Buses
Krishnan Sundaresan, Michigan State University
Nihar R. Mahapatra, Michigan State University
Distributing the Frontend for Temperature Reduction
Pedro Chaparro Monferrer, Universitat Politecnica de
Catalunya and Intel Labs
Grigorios Magklis, Universitat Politecnica de Catalunya
and Intel Labs
Jose Gonzalez, Universitat Politecnica de Catalunya and
Intel Labs
Antonio Gonzalez, Universitat Politecnica de Catalunya
and Intel Labs
Performance, Energy, and Thermal Considerations for SMT and CMP
Architectures
Yingmin Li University of Virginia
David Brooks Harvard University
Zhigang Hu IBM T.J.Watson Research Center
Kevin Skadron University of Virginia
Tapping ZettaRAM for Low-Power Memory Systems
Ravi K. Venkatesan, North Carolina State University
Ahmed S. AL-Zawawi, North Carolina State University
Eric Rotenberg, North Carolina State University
3:30-4:00 Break
4:00-6:00 SESSION 3: COMMUNICATION ARCHITECTURES
Chair: Timothy Pinkston, University of Southern California
An Efficient Programmable 10 Gigabit Ethernet Network Interface Card
Paul Willmann, Rice University
Hyong-youb Kim, Rice University
Scott Rixner, Rice University
Vijay S. Pai, Purdue University
A New Scalable and Cost-Effective Congestion Management Strategy for
Lossless Multistage Interconnection Networks
J. Duato, Universitat Politecnica de Valencia, Spain
I. Johnson, Xyratex, United Kingdom
J. Flich, Universitat Politecnica de Valencia, Spain
F. Naven, Xyratex, United Kingdom
P. Garcï¿&fraq12;a, Universidad de Castilla-La Mancha, Spain
T. Nachiondo, Universitat Politecnica de Valencia, Spain
Exploring the Design Space of Power-Aware Opto-Electronic Networked
Systems
Xuning Chen, Princeton University
Yue-kai Huang, Princeton University
Li-Shiuan Peh, Princeton University
Paul Prucnal, Princeton University
Gu-Yeon Wei, Harvard University
Scatter-Add in Data Parallel Architectures
Jung Ho Ahn, Stanford University
Mattan Erez, Stanford University
Bill Dally, Stanford University
6:30-8:00 TCCA Business Meeting
Tuesday February 15, 2004
8:00-10:00 SESSION 4: ENERGY AND POWER
Chair: Yuanyuan Zhou, University of Illinois
Software Assisted Issue Queue Power Reduction
Timothy M. Jones, University of Edinburgh
Michael F. P. O'Boyle, University of Edinburgh
Jaume Abella, Universitat Politecnica de Catalunya
Antonio Gonzalez, Universitat Politecnica Catalunya and Intel Labs
On the Limits of Leakage Power Reduction in Caches
Yan Meng, University of California, Santa Barbara
Timothy Sherwood, University of California, Santa Barbara
Ryan Kastner, University of California, Santa Barbara
Heat Stroke: Power-Density-Based Denial of Service in SMT
Jahangir Hasan, Purdue University
Ankit Jalote, Purdue University
T. N. Vijaykumar, Purdue University
Carla Brodley, Tufts University
Voltage and Frequency Control with Adaptive Reaction Time in
Multiple-Clock-Domain Processors
Qiang Wu, Princeton University
Philo Juang, Princeton University
Margaret Martonosi, Princeton University
Douglas W. Clark, Princeton University
10:00-10:30 Break
10:30-12:30 SESSION 5: MEMORY SYSTEM ISSUES
Chair: John Carter, University of Utah
Using Virtual Load/Store Queues (VLSQs) to Reduce the
Negative Effects of Reordered Memory Instructions
Aamer Jaleel, University of Maryland, College Park
Bruce Jacob, University of Maryland, College Park
A Unified Compressed Memory Hierarchy
Erik Hallnor, University of Michigan
Steven Reinhardt, University of Michigan
A Performance Comparison of DRAM Memory System Optimizations for SMT
Processors
Zhichun Zhu, University of Illinois at Chicago
Zhao Zhang, Iowa State University
Effective Instruction Prefetching in Chip
Multiprocessors for Modern Commercial Applications
Lawrence Spracklen, Sun Microsystems
Yuan Chou, Sun Microsystems
Santosh G. Abraham, Sun Microsystems
12:30-1:30 Lunch (Provided)
1:30-3:30 SESSION 6: INDUSTRIAL PERSPECTIVES (I)
Chair: Sanjay Patel, University of Illinois
Stretching the Limits of Clock-Gating Efficiency in
Server-Class Processors
Hans Jacobson, Pradip Bose, Zhigang Hu, Alper Buyuktosunoglu,
Victor Zyuban, Rick Eickemeyer, Lee Eisen, John Griswell,
Doug Logan, Balaram Sinharoy, Joel Tendler, IBM
The Soft Error Problem: An Architectural Perspective
Shubu Mukherjee, Intel
Joel Emer, Intel
Steven Reinhardt, University of Michigan
Chip Multithreading: Opportunities and Challenges
Lawrence Spracklen, Sun Microsystems
Santosh G. Abraham, Sun Microsystems
Enterprise IT Trends and Implications for Architecture Research
Parthasarathy Ranganathan, HP Labs
Norman Jouppi, HP Labs
3:30-4:00 Break
4:00-6:00 SESSION 7: INDUSTRIAL PERSPECTIVES (II)
Chair: Wen-Mei Hwu, University of Illinois
The Cell Processor
Peter Hofstee, IBM
Panel: New Opportunities for Computer Architecture Research: An
Industrial
Perspective
Organizer: Wen-Mei Hwu, University of Illinois
7:00-10:00 Evening Social Activity: Boat Tour of the San Francisco Bay
Wednesday February 16, 2004
8:00-9:00 SESSION 8: EVALUATION METHODOLOGIES
Chair: Pradip Bose, IBM
Characterizing and Comparing Prevailing Simulation Techniques
Joshua J. Yi, Freescale Semiconductor
Sreekumar V. Kodakara, University of Minnesota
Resit Sendag, University of Rhode Island
David J. Lilja, University of Minnesota
Douglas M. Hawkins, University of Minnesota
Transition Phase Classification and Prediction
Jeremy Lau, University of California, San Diego
Stefan Schoenmackers, University of California, San Diego
Brad Calder, University of California, San Diego
9:00-10:00 SESSION 9: SOFTWARE DEBUGGING SUPPORT
Chair: Yan Solihin, North Carolina State University
SafeMem: Exploiting ECC-Memory for Detecting Memory Leaks and
Memory Corruption During Production Runs
Feng Qin, University of Illinois
Shan Lu, University of Illinios
Yuanyuan Zhou, University of Illinois
Low-Overhead Interactive Debugging via Dynamic Instrumentation with DISE
Marc L. Corliss, University of Pennsylvania
E. Christopher Lewis, University of Pennsylvania
Amir Roth, University of Pennsylvania
10:00-10:30 Break
10:30-12:30 SESSION 10: MULTIPROCESSORS AND MULTITHREADING
Chair: Christos Kozyrakis, Stanford University
Unbounded Transactional Memory
C. Scott Ananian, MIT
Krste Asanovic, MIT
Bradley C. Kuszmaul, MIT
Charles E. Leiserson, MIT
Sean Lie, MIT
Improving Multiple-CMP Systems Using Token Coherence
Michael R. Marty, University of Wisconsin-Madison
Jesse D. Bingham, University of British Columbia
Mark D. Hill, University of Wisconsin-Madison
Alan J. Hu, University of British Columbia
Milo M.K. Martin, University of Pennsylvania
David A. Wood, University of Wisconsin-Madison
Predicting Inter-Thread Cache Contention on a Chip Multi-Processor
Architecture
Dhruba Chandra, North Carolina State University
Fei Guo, North Carolina State University
Seongbeom Kim, North Carolina State University
Yan Solihin, North Carolina State University
SENSS: Security Enhancement to Symmetric Shared Memory Multiprocessors
Youtao Zhang, University of Texas at Dallas,
Lan Gao, University of California, Riverside,
Jun Yang, University of California, Riverside,
Xiangyu Zhang, University of Arizona
Rajiv Gupta, University of Arizona
12:30 End of Conference
June 27-30, 2005
Monte Carlo Resort, Las Vegas, Nevada, USA
! ! NEW: Keynotes and focus sessions ! !