Happy Holidays!
Welcome to IEEE TCCA Email-Monthly, Dec. 2002:
Computer Architecture
submitted by: Soner Onder <soner@mtu.edu>
CALL FOR PARTICIPATION http://www.cs.arizona.edu/hpca9
2. MAPLD 6th Military and Aerospace Programmable Logic Device
International Conferences
submitted by: Richard B. Katz mapld2003@klabs.org
Call for Paper
http://klabs.org/richcontent/MAPLDCon03/admin/mapldcon03_cfp .html
3. THE ELEVENTH ANNUAL IEEE SYMPOSIUM ON FIELD PROGRAMMABLE
CUSTOM COMPUTING MACHINES
Submitted by Jeffrey Arnold <jmarnold@znet.com>
CALL FOR PAPERS http://www.fccm.org
send an email to
qyang@ele.uri.edu
<http://www.computer.org/TCsignup/index.htm>
Distinguished Engineering Professor e-mail: qyang@ele.uri.edu Dept. of Electr. & Comput. Engineering Tel. (401) 874-5880 University of Rhode Island Fax (401) 782-6422 Kingston RI. 02881 http://www.ele.uri.edu/~qyang
~~~~~~~~~~~~~~~~~~~~~~~~~~~~Message Details~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
HPCA - 9
Anaheim, California
February 8-12, 2003
The International Symposium on High-Performance Computer Architecture provides a high quality forum for scientists and engineers to present their latest research findings in this rapidly changing field. HPCA-9, the ninth in the series of International Symposium on High Performance Computer Architecture, will be held in Anaheim, California.
Please visit the conference web page at:
http://www.cs.arizona.edu/hpca9
ON-LINE REGISTRATION is now OPEN.
EARLY REGISTRATION DEADLINE: 5:00pm Eastern FRIDAY, JANUARY 17, 2003.
INTERACT-7 The 7th Annual Workshop on Interaction between Compilers and Computer Architecture
SAN-2 2nd Annual Workshop on Novel Uses of System Area Networks
An introduction to Network Processors Patrick Crowley, U. Washington
CAECW Sixth Workshop on Computer Architecture Evaluation using Commercial Workloads
NP-2 The Second Workshop on Network Processors
SSRS Workshop on Software Support for Reconfigurable Systems
Tutorial (Morning)
New Computing Platforms for Embedded Systems Frank Vahid & Walid Najjar, U. California Riverside
Simics Microarchitect's Toolset Peter Magnuson, Virtutech
Billion Transistor Chips in Mainstream Enterprise Platforms of
the Future
Dileep Bhandarkar
Architect-at-large, Enterprise Platforms Group, Intel Corporation
Variability in Architectural Simulations of Multi-threaded
Workloads
Alaa Alameldeen and David Wood
Mini-threads: Increasing TLP on Small-Scale SMT Processors
Joshua Redstone, Susan Eggers, and Henry Levy
Front-End Policies for Improved Issue Efficiency in SMT
Processors
Ali El-Moursy and David Albonesi
Reconsidering Complex Branch Predictors
Daniel Jimenez
Incorporating Predicate Information Into Branch Predictors
Beth Simon, Brad Calder, and Jeanne Ferrante
Dynamic Data Dependence Tracking and its Application to Branch
Prediction
Lei Chen, Steve Dropsho, and David Albonesi
Control Techniques to Eliminate Voltage Emergencies in
High-Performance Processors
Russ Joseph, David Brooks, and Margaret Martonosi
Dynamic Voltage Scaling with Links for Power Optimization of
Interconnection Networks
Li Shang, Li-Shiuan Peh, and Niraj Jha
Power-Aware Control Speculation through Selective Throttling
Juan L. Aragon, Jose Gonzalez, and Antonio Gonzalez
Deterministic Clock Gating For Microprocessor Power Reduction
Hai Li, Swarup Bhunia, Yiran Chen, Kaushik Roy, and
T.N. Vijaykumar
BANQUET
Beyond Performance: Some (other) Challenges for Future
Microprocessors.
Eric Kronstadt
Director, VLSI Systems, IBM TJ Watson
Runahead Execution: An Alternative to Very Large Instruction
Windows for Out-of-order Processors
Onur Mutlu, Jared Stark, Chris Wilkerson, and Yale Patt
Microarchitecture and Performance Analysis of a SPARC-V9
Microprocessor for Enterprise Server Systems
Mariko Sakamoto, Akira Katsuno, Alichiro Inoue, Takeo Asakawa,
Haruhiko Ueno, and Kuniki Morita
Exploring the VLSI Scalability of Stream Processors
Brucek Khailany, William J. Dally, Scott Rixner, Ujval J. Kapasi,
John Owens, and Brain Towles
Dynamic Optimization Of Micro-Operations
Brian Slechta, Brian Fahs, David Crowe, Michael Fertig,
Gregory Muthler, Justin Quek Francesco Spadini,
Sanjay J. Patel, and Steven S. Lumetta
Luncheon (12:00n - 1:30pm)
Slipstream Execution Mode for CMP-Based Multiprocessors
Khaled Ibrahim, Gregory Byrd, and Eric Rotenberg
Tradeoffs in Buffering Memory State for Thread-Level Speculation
in Multiprocessors
Maria Garzaran, Milos Prvulovic, Victor Vinals, Jose Llaberia,
Lawrence Rauchwerger, and Josep Torrellas
Dynamic Data Replication: An approach to Providing Fault-Tolerant
Shared Memory Clusters
Rosalia Christodoulopoulou, Reza Azimi, and Angelos Bilas
Memory System Behavior of Java-Based Middleware
Martin Karlsson, Kevin Moore, Erik Hagersten, and David Wood
Evaluating the Impact of Communication Architecture on the
Performability of Cluster-Based Services
Kiran Nagaraja, Neeraj Krishnan, Ricardo Bianchini,
Richard Martin, and Thu Nguyen
Hierarchical Back-Off Lock for Non-Uniform Communication
Architectures
Zoran Radovic and Erik Hagersten
Performance Enhancement Techniques for InfiniBand Architecture
Eun Jung Kim, Ki Hwan Yum, Chita Das, Mazin Yousif,
and Jose Duato
The State of State
Peter Kogge
McCourtney Professor of Computer Science and Engineering,
University of Notre Dame
Catching Accurate Profiles in Hardware
Satish Narayanasamy, Timothy Sherwood, Suleyman Sair,
Brad Calder, and George Varghese
A Statistically Rigorous Approach for Improving Simulation
Methodology
Joshua Yi, David Lilja, and Douglas Hawkins
Caches and Merkle Trees for Efficient Memory Authentication
Blaise Gassend, Ed Suh, Dwaine Clarke, Marten van Dijk,
and Srinivas Devadas
Just Say No: Benefits of Early Cache Miss Determination
Gokhan Memik, Glenn Reinman, and William Mangione-Smith
TCP: Tag Correlating Prefetchers
Zhigang Hu, Stefanos Kaxiras, and Margaret Martonosi
Cost-sensitive Cache Replacement Algorithms
Jaeheon Jeong and Michel Dubois
Scalar Operand Networks
Michael Taylor, Walter Lee, Saman Amarasinghe, and
Anant Agarwal
Inter-cluster Communication Models for Clustered VLIW processors
Andrei Terechko, Erwan Le Thenaff, Manish Garg,
Jos van Eijndhoven, and Henk Corporaal
A Methodology for Designing Efficient On-Chip Interconnects
on Well-behaved Communication Patterns
Wai Hong Ho and Timothy Pinkston
Active I/O Switches in System Area Networks
Ming Hao and Mark Heinrich
Title: 6th Military and Aerospace Programmable Logic Device (MAPLD)
International Conferences
Short Description: The Military and Aerospace Programmable Logic Device (MAPLD) International Conferences present papers on programmable devices and technologies, as well as digital engineering and related fields. Devices, technologies, logic design, flight applications, fault tolerance, usage, reliability, radiation susceptibility, and encryption applications of programmable devices, processors, and adaptive computing systems in military and aerospace systems are topics for papers.
Link: http://klabs.org/mapld
Call for Papers: http://klabs.org/richcontent/MAPLDCon03/admin/mapldcon03_cfp .html
Date: September 9-11, 2003
Location: Reagan Reagan Building and International Trade Center,
Washington, D.C.
Contact Info: Richard B. Katz
National Aeronautics and Space Administration
mapld2003@klabs.org
C A L L F O R P A P E R S
THE ELEVENTH ANNUAL
IEEE SYMPOSIUM ON FIELD PROGRAMMABLE
CUSTOM COMPUTING MACHINES
Napa Valley, California
April 8 - April 11, 2003
http://www.fccm.org
PURPOSE: To bring together researchers to present recent work in the use of reconfigurable logic as computing elements. This symposium will focus primarily on the current opportunities and problems in this new and evolving technology for computing. Contributions are solicited on all aspects of custom computing, including but not limited to:
Architecture of reconfigurable computing devices and systems, including coprocessors, attached processors, reconfigurable systems-on-chip and hybrids;
Languages, compilation techniques, tools, and environments for programming and run time support;
Applications of reconfigurable computing, including the use of reprogrammable logic in mobile communications, network infrastructure and other embedded systems;
Implications of nanotechnology and reconfigurable computing on one another, possible forms, system implications, use of reconfiguration to support fault avoidance;
Novel use of reconfigurability, including evolvable hardware;
Prototyping for system modeling and architecture emulation.
SUBMISSIONS: FCCM has a tradition of presenting both full length papers and high quality posters. Authors are invited to send submissions for either full length papers (10 page maximum) or extended abstracts (2 page maximum) for posters by January 13, 2003, to Jeffrey Arnold. Please indicate whether you seek consideration as a full paper or as a poster. Notification of acceptance will be sent by the beginning of March. Final papers and poster abstracts will be due on the first day of the Symposium. The proceedings will be published following the Symposium.
Authors are encouraged to submit PDF or Postscript manuscripts by FTP. Format and submission instructions are available on the FCCM web page (www.fccm.org), or authors can contact Jeffrey Arnold (jmarnold@ieee.org).
Authors are also encouraged to bring demonstrations of their work. Space will be made available during the demo event to be held Wednesday, April 9. Details will be available on the web page.
SPONSORSHIP: The IEEE Computer Society and the Technical Committee on Computer Architecture.
CO-CHAIRS:
Kenneth L. Pocek
Intel
Mail Stop RN6-18
2200 Mission College Boulevard
Santa Clara, California 95052
Voice: 408-765-6705 Fax: 408-765-5165
kenneth.pocek@intel.com
Jeffrey M. Arnold
Stretch, Inc.
10686 Mira Lago Terrace
San Diego, CA 92131
Voice: 858-547-9257 Fax: 858-547-9010
jmarnold@ieee.org
PROGRAM COMMITTEE:
Peter Athanas, Virginia Tech.
Donald Bouldin, University of Tennessee, Knoxville
Duncan Buell, University of South Carolina
Michael Butts, Cadence
Steve Casselman, Virtual Computer Corp.
Andre DeHon, California Institute of Technology
Apostolos Dollas, Technical Univ. of Crete
Philip Friedin, Fliptronics
Scott Hauck, University of Washington
Brad Hutchings, Brigham Young Univ.
Tom Kean, Algotronix, Ltd.
Phil Kuekes, HP Labs.
Philip Leong, Chinese University of Hong Kong
Wayne Luk, Imperial College
John McHenry, NSA
Robert Parker, Institute for Information Sciences
Viktor Prasanna, University of Southern California
Herman Schmit, Carnegie Mellon University
Mark Shand, HP Labs
Satnam Singh, Xilinx
Stephen Smith, Lochran
Roger Woods, The Queen's University of Belfast