See the complete IDE standard document.
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Signals:
6.3.1 CS1FX- (drive chip select 0)
This is the chip select signal decoded from the host address bus used
to
select the Command Block Registers.
6.3.2 CS3FX- (drive chip select 1)
This is the chip select signal decoded from the host address bus used
to
select the Control Block Registers.
6.3.3 DA0-2 (Drive address bus)
This is the 3-bit binary coded address asserted by the host to access
a
register or data port in the drive.
6.3.4 DASP- (Drive active/drive 1 present)
This is a time-multiplexed signal which indicates that a drive is active,
or
that Drive 1 is present. This signal shall be an open collector output
and
each drive shall have a 10K ohm pull-up resistor.
During power on initialization or after RESET- is negated, DASP- shall
be
asserted by Drive 1 within 400 msec to indicate that Drive 1 is present.
Drive 0 shall allow up to 450 msec for Drive 1 to assert DASP-. If
Drive 1
is not present, Drive 0 may assert DASP- to drive an activity LED.
DASP- shall be negated following acceptance of the first valid command
by
Drive 1 or after 31 seconds, whichever comes first.
Any time after negation of DASP-, either drive may assert DASP- to
indicate
that a drive is active.
NOTE 1 - Prior to the development of this standard, products were introduced
which did not time multiplex DASP-. Some used two jumpers to indicate
to Drive
0 whether Drive 1 was present. If such a drive is jumpered to indicate
Drive
1 is present it should work successfully with a Drive 1 which complies
with this
standard. If installed as Drive 1, such a drive may not work successfully
because it may not assert DASP- for a long enough period to be recognized.
However, it would assert DASP-to indicate that the drive is active.
6.3.5 DD0-DD15 (Drive data bus)
This is an 8- or 16-bit bidirectional data bus between the host and
the drive.
The lower 8 bits are used for 8-bit transfers e.g., registers, ECC
bytes and,
if the drive supports the Features Register capability to enable 8-bit-only
data transfers (see 9.22).
6.3.6 DIOR- (Drive I/O read)
This is the Read strobe signal. The falling edge of DIOR- enables data
from
a register or the data port of the drive onto the host data bus, DD0-DD7
or
DD0-DD15. The rising edge of DIOR- latches data at the host.
6.3.7 DIOW- (Drive I/O write)
This is the Write strobe signal. The rising edge of DIOW- clocks data
from
the host data bus, DD0-DD7 or DD0-DD15, into a register or the data
port of
the drive.
6.3.8 DMACK- (DMA acknowledge) (Optional)
This signal shall be used by the host in response to DMARQ to either
acknowledge that data has been accepted, or that data is available.
6.3.9 DMARQ (DMA request) (Optional)
This signal, used for DMA data transfers between host and drive, shall
be
asserted by the drive when it is ready to transfer data to or from
the host.
The direction of data transfer is controlled by DIOR- and DIOW-. This
signal
is used in a handshake manner with DMACK- i.e., the drive shall wait
until the
host asserts DMACK- before negating DMARQ, and re-asserting DMARQ if
there is
more data to transfer.
When a DMA operation is enabled, IOCS16-, CS1FX-, and CS3FX- shall
not be
asserted and transfers shall be 16-bits wide.
NOTE 2 - ATA products with DMA capability require a pull-down resistor
on this
signal to prevent spurious data transfers. This resistor may affect
driver
requirements for drives sharing this signal in systems with unbuffered
ATA
signals.
6.3.10 INTRQ (Drive interrupt)
This signal is used to interrupt the host system. INTRQ is asserted
only when
the drive has a pending interrupt, the drive is selected, and the host
has
cleared nIEN in the Device Control Register. If nIEN=1, or the drive
is not
selected, this output is in a high impedance state, regardless of the
presence
or absence of a pending interrupt.
INTRQ shall be negated by:
- assertion of RESET- or;
- the setting of SRST of the Device Control Register, or;
- the host writing the Command Register or;
- the host reading the Status Register.
NOTE 3 - Some drives may negate INTRQ on a PIO data transfer completion,
except
on a single sector read or on the last sector of a multi-sector read.
On PIO transfers, INTRQ is asserted at the beginning of each data block
to be
transferred. A data block is typically a single sector, except when
declared
otherwise by use of the Set Multiple command. An exception occurs on
Format
Track, Write Sector(s), Write Buffer and Write Long commands - INTRQ
shall not
be asserted at the beginning of the first data block to be transferred.
On DMA transfers, INTRQ is asserted only once, after the command has
completed.
6.3.11 IOCS16- (Drive 16-bit I/O)
Except for DMA transfers, IOCS16- indicates to the host system that
the 16-bit
data port has been addressed and that the drive is prepared to send
or receive
a 16-bit data word. This shall be an open collector output.
- When transferring in PIO mode, if IOCS16- is not asserted, transfers
shall be 8-bit using DD0-7.
- When transferring in PIO mode, if IOCS16- is asserted, transfers
shall
be 16-bit using DD0-15.
- When transferring in DMA mode, the host shall use a 16-bit DMA channel
and IOCS16- shall not be asserted.
6.3.12 IORDY (I/O channel ready) (Optional)
This signal is negated to extend the host transfer cycle of any host
register
access (Read or Write) when the drive is not ready to respond to a
data
transfer request. When IORDY is not negated, IORDY shall be in a high
impedance state.
6.3.13 PDIAG- (Passed diagnostics)
This signal shall be asserted by Drive 1 to indicate to Drive 0 that
it has
completed diagnostics. A 10K ohm pull-up resistor shall be used on
this
signal by each drive.
Following a power on reset, software reset or RESET-, Drive 1 shall
negate
PDIAG- within 1 msec (to indicate to Drive 0 that it is busy). Drive
1 shall
then assert PDIAG- within 30 seconds to indicate that it is no longer
busy,
and is able to provide status. If Drive 1 is present, then Drive 0
shall wait
for up to 31 seconds from power-on reset, software reset or RESET-
for Drive
1 to assert PDIAG-. If Drive 1 fails to assert PDIAG-, Drive 0 shall
set bit
7 to 1 in the Error Register to indicate that Drive 1 failed. After
the
assertion of PDIAG-, Drive 1 may be unable to accept commands until
it has
finished its reset procedure and is Ready (DRDY=1).
Following the receipt of a valid Execute Drive Diagnostics command,
Drive 1
shall negate PDIAG- within 1 msec to indicate to Drive 0 that it is
busy and
has not yet passed its drive diagnostics. Drive 1 shall then assert
PDIAG-within
5 seconds to indicate that it is no longer busy, and is able to provide
status. Drive 1 should clear BSY before asserting PDIAG-. If Drive
1 is
present then Drive 0 shall wait for up to 6 seconds from the receipt
of a
valid Execute Drive Diagnostics command for Drive 1 to assert PDIAG-.
If
Drive 1 fails to assert PDIAG-, Drive 0 shall set bit 7 to 1 in the
Error
Register to indicate that Drive 1 failed.
If DASP- was not asserted by Drive 1 during reset initialization, Drive
0
shall post its own status immediately after it completes diagnostics,
and
clear the Drive 1 Status Register to 00h. Drive 0 may be unable to
accept
commands until it has finished its reset procedure and is Ready (DRDY=1).
6.3.14 RESET- (Drive reset)
This signal from the host system shall be asserted for at least 25
usec after
voltage levels have stabilized during power on and negated thereafter
unless
some event requires that the drive(s) be reset following power on.
6.3.15 SPSYNC:CSEL (Spindle synchronization/cable select) (Optional)
This signal shall have a 10K ohm pull-up resistor.
This is a dual purpose signal and either or both functions may be implemented.
If both functions are implemented then they cannot be active concurrently:
the
choice as to which is active is made by a vendor-defined switch.
All drives connected to the same cable should have the same function
active
at the same time. If SPSYNC and CSEL are mixed on the same cable, then
drive
behavior is undefined.
Prior to the introduction of this standard, this signal was defined
as DALE
(Drive Address Latch Enable), and used for an address valid indication
from
the host system. If used, the host address and chip selects, DAO through
DA2,
CS1FX-, and CS3FX- were valid at the negation of this signal and remained
valid while DALE was negated, therefore, the drive did not need to
latch these
signals with DALE.
6.3.16 SPSYNC (Spindle synchronization) (Optional)
This signal may be either input or output to the drive depending on
a
vendor-defined switch. If a drive is set to Master the signal is output,
and
if a drive is set to slave the signal is input.
There is no requirement that each drive implementation be plug-compatible
to
the extent that a multiple vendor drive subsystem be operable. Mix
and match
of different manufacturers drives is unlikely because rpm, sync fields,
sync
bytes, etc., need to be virtually identical. However, if drives are
designed
to match the following recommendation, controllers can operate drives
with a
single implementation.
There can only be one master drive at a time in a configuration. The
host or
the drive designated as master can generate SPSYNC at least once per
rotation,
but may be at a higher frequency.
SPSYNC received by a drive is used as the synchronization signal to
lock the
spindles in step. The time to achieve synchronization varies, and is
indicated by the drive setting DRDY i.e., if the drive does not achieve
synchronization following power on or a reset, it shall not set DRDY.
A master drive or the host generates SPSYNC and transmits it.
A slave drive does not generate SPSYNC and is responsible to synchronize
its
index to SPSYNC.
If a drive does not support synchronization, it shall ignore SPSYNC.
In the event that a drive previously synchronized loses synchronization,
but
is otherwise operational, it does not clear DRDY.
6.3.17 CSEL (Cable select) (Optional)
The drive is configured as either Drive 0 or Drive 1 depending upon
the value
of CSEL:
- If CSEL is grounded then the drive address is 0;
- If CSEL is open then the drive address is 1.
Special cabling can be used by the system manufacturer to selectively
ground
CSEL e.g., CSEL of Drive 0 is connected to the CSEL conductor in the
cable,
and is grounded, thus allowing the drive to recognize itself as Drive
0. CSEL
of Drive 1 is not connected to CSEL because the conductor is removed,
thus the
drive can recognize itself as Drive 1. See figure 5.
+------ CSEL Conductor -------------------------+
| | Open
|Ground | |
+------+ +---------+ +---------+
| Host | | Drive 0 | | Drive 1 |
+------+ +---------+ +---------+
+------ CSEL Conductor -------------------------+
| Open |
|Ground | |
+------+ +---------+ +---------+
| Host | | Drive 1 | | Drive 0 |
+------+ +---------+ +---------+
Figure 5 - Cable select