Michael Vilnit
Scott Wiant
ELE 408
Final Project
Performance and Cost Evaluation of ColdFire Evaluation Boards
Introduction:
For our project, we performed a performance and cost evaluation of the various ColdFire evaluation boards currently on the market. This included the MCF5102, MCF5202, MCF 5204, MCF 5206, MCF 5206e, and MCF 5307. We researched each board and found the ones that were best suited for various common tasks.
This project differed slightly from our original proposal. We initially had planned on designing programs to test the capabilities of the boards but we soon realized that this would be impossible since we could only run these programs on the MCF5307. This wouldn’t allow us to draw any conclusions about the relative performance of the other boards and wouldn’t provide useful information.
We determined that the best approach to this project would be to research each of the individual boards. We then drew upon our knowledge from class to determine what attributes of each board would make it best suited for individual tasks. We polled vendors and obtained design specifications from the Motorola web site in order to come to conclusions about the various ColdFire evaluation boards relative performance.
Procedure:
MCF5102:
The MCF5102 was the inaugural board in the ColdFire series. It was fully backwards compatible with the previous 68K series of Motorola processors. This allowed it to utilize all the software tools that had been developed for the boards that came before it.
Compared to the next three boards that Motorola released, this one performed surprisingly better. It was able of reaching speeds of 44 MIPS at 40MHz. It was the only board in the series that had the cache spilt into two parts. 1K of cache was designated for data and 2K was for instructions. This was implemented in a 4-way set associative manner.
The one drawback of this board was that it didn’t include any of the additional modules that were designed for the boards that followed. This included a DMA controller, a DRAM controller, a timer, a UART or a NIC. This allowed it to be fairly inexpensive, costing only $24.40.
MCF5202:
Motorola developed a second core version when they designed the MCF5202. It included a 2K unified cache and a debug module for software support. Compared to the MCF5102, the performance wasn’t as good. It performed 25MIPS at 33MHz. The 5202 also cost a lot less, having a $11.64 price tag.
This board also provided the best performance for the money. When we performed a cost vs. performance evaluation of the ColdFire boards, the 5202 came out on top. It cost only $.46 per MIP.
MCF5204:
The MCF5204 also used the ColdFire Core Version 2. In an attempt to conserve the cost, the cache was cut to 512K of direct mapped cache. The advantages of this board were the additional modules that were implemented. It contains a UART for serial transmissions and a timer for time intensive programs.
The only drawback of this board was that it doesn’t perform as well as they other boards. It only executes 13.5MIPS at 33MHz. Despite this, it still cost just as much as the other boards.
MCF5206:
The MCF5206 also didn’t show any significant performance improvements over the previous boards. It performed 17MIPS at 33 MHz. Coupled with its $18.38 price tag it doesn’t appear to be very cost effective either. Once again, the price increase was due to new technology implemented in the board.
The 5206 contained a DRAM controller that allowed users to add up to 512 Mbytes of additional DRAM. This greatly increased the memory capacity of the board. A second UART was also added to allow bi-directional serial transfers.
MCF5206e:
The
last edition of the ColdFire series using the Version 2 Core was the MCF5206e.
With this release, Motorola decided that performance improvements were just as
important as adding additional functionality. The 5206e performed 50MIPS at
54MHz. It also included a Multiply
Accumulate Unit and Hardware Divide Module to perform high speed
complex arithmetic functions, a two-channel DMA controller and 4 Kbytes of
direct mapped cache. It was also the first board to have SRAM on the processor.
It contained 8 Kbytes RAM on the chip.
Unfortunately, the
MCF5206e is as available as Motorola’s other processors. Of the 6 vendors that
we spoke with, only one carried this board. It also cost considerably more than
the other processors, $35.40.
MCF5307:
The most recent Motorola evaluation board, the MCF5307, utilized the ColdFire Core Version 3. Its major improvement was an 8-instruction FIFO buffer for pipelining. It also is the first processor to utilize 8K of unified, 4 way set associative cache. In addition, it had 4 Kbytes of on-chip SRAM, a 2-channel DMA controller, two full duplex UARTs and performed 75MIPS at 90MHz.
Once again, the MCF55307 was only carried
by one of the 6 vendors that we spoke with. According to this vendor, not many
people require all the functionality that the board offers. Unless all of it’s
additional hardware is required, it’s probably not worth spending $45.20 for
it.
Results and Conclusion:
After reviewing the various board
configurations and functionality, we determined that the best ColdFire
Processor for the task really depends on what the task is. From one board to
the next, many things are added or taken away (See Figure 1.1 – 1.3 in the
appendix). In order to decide which board is best suited for you, you have to
take into consideration what exactly your task requires.
• Direct Memory
Access Controller to quickly and
efficiently move blocks of data.
• DRAM controller to integrate DRAM with the ColdFire
product.
• UART for serial transmissions
• Timer for time constrained applications.
• Debug module for programming ease.
• Ethernet controller for networking applications.
• Hardware implementation of mathematical operations
If money isn’t an
object, I would recommend the MCF5307 due to the fact that it has all the
functionality of the previous boards and runs at much higher speeds. But if
money isn’t an object, then you have to decide on what features you can do
without and find the best processor that you can afford. If it comes down to
just processing, then the MCF5202 is definitely your best bet (See Figure 4).
Constraints:
Economic Constraints:
As stated above,
depending on the intended use of the microprocessor, one model of the Cold Fire
chip may be more cost effective than another. If you need to move large blocks
of data, you would want to use the MCF5306e or the MCF5307 due to the fact that
it includes a DMA controller. If memory concerns are an issue than you would
want to use the MCF5206, MCF5306e or the MCF5307 to utilize its DRAM controller
and its extended memory. If you need to communicate with other processors, over
a LAN or over the Internet, you would want a MCF5204 due to the fact that they
contain a UART and/or a NIC.
Manufacturability, Modularity and Expandability Constraints:
If modularity is a concern, then you would want to purchase a board that would allow multiple processors to work on a single task. This could possibly be implemented using the NIC and multiple boards to achieve parallelism.
If you believe that you might need additional storage, then you would want to purchase a board that contains a DRAM controller. If your program requires more than the 512 Mbytes of memory that the DRAM controller offers, then you might want to consider optimizing your code or talk to Roland about his hard drive controller that he designed.
Health and Safety Constraints:
Although there is not a serious health risk directly caused by any of the Motorola processors, our results could be used in a situation that would affect the safety of another embedded system. This being the case, our results will only come out after thorough testing, evaluation, and research.
Social and Political Constraints:
N/A
Appendix:
Figure 1.1:
|
|
5102 |
5202 |
|
MIPs |
44 at 40Mhz |
25 at 33MHz |
|
MHz |
up to 40Mhz |
up to 33 MHz |
|
Bus Speed |
up to 20 MHz |
up to 16 MHz |
|
Core Version |
1 |
2 |
|
Instruction Set |
Variable Length RISC |
Variable Length RISC |
|
Pipelining |
2 Stage Instruction, 2 Stage Operand |
2 Stage Instruction, 2 Stage Operand |
|
|
3 Instruction FIFO Buffer |
3 Instruction FIFO Buffer |
|
Address Bus |
Dynamic Bus Sizing (32,16, or 8 bit) |
Dynamic Bus Sizing (32,16, or 8 bit) |
|
Data Bus |
Dynamic Bus Sizing (32,16, or 8 bit) |
Dynamic Bus Sizing (32,16, or 8 bit) |
|
Registers |
16, 32bit user accessible registers |
16, 32bit user accessible registers |
|
Cache |
1K Data, 2K Instruction, 4-Way Set Associative |
2K Unified 4-Way Set Associative Cache |
|
DMA |
No |
No |
|
DRAM |
No |
No |
|
UART |
No |
No |
|
TIMER |
No |
No |
|
Debug Module |
No |
Yes |
|
Multiply-Accumulate Unit |
No |
No |
|
Hardware Divide Module |
No |
No |
|
SRAM |
None |
None |
Figure 1.2:
|
|
5204 |
5206 |
|
MIPs |
13.5 at 33MHz |
17 at 33MHz |
|
MHz |
up to 33 MHz |
up to 33 MHz |
|
Bus Speed |
up to 16 MHz |
up to 16 MHz |
|
Core Version |
2 |
2 |
|
Instruction Set |
Variable Length RISC |
Variable Length RISC |
|
Pipelining |
2 Stage Instruction, 2 Stage Operand |
2 Stage Instruction, 2 Stage Operand |
|
|
3 Instruction FIFO Buffer |
3 Instruction FIFO Buffer |
|
Address Bus |
32-bit w/ 4 Mbytes linear address space |
32-bit w/ 256 Mbytes linear address space |
|
Data Bus |
16 Bit |
32 Bit |
|
Registers |
16, 32bit user accessible registers |
16, 32bit user accessible registers |
|
Cache |
512 Bytes Direct-Mapped Instruction Cache |
512 Bytes Direct-Mapped Instruction Cache |
|
DMA |
No |
No |
|
DRAM |
No |
Yes |
|
UART |
1 |
2 |
|
TIMER |
2 16 Bit Timers |
2 16 bit Timers |
|
Debug Module |
Yes |
Yes |
|
Multiply-Accumulate Unit |
No |
No |
|
Hardware Divide Module |
No |
No |
|
SRAM |
512 Byte |
512 Byte |
Figure 1.3:
|
|
5206e |
5307 |
|
MIPs |
50 at 54MHz |
70 at 90MHz |
|
MHz |
up to 54MHz |
up to 90MHz |
|
Bus Speed |
up to 27MHz |
up to 45MHz |
|
Core Version |
2 |
3 |
|
Instruction Set |
Variable Length RISC |
Variable Length RISC |
|
Pipelining |
2 Stage Instruction, 2 Stage Operand |
4 Stage Instruction, 2 Stage Operand |
|
|
3 Instruction FIFO Buffer |
8 Instruction FIFO Buffer |
|
Address Bus |
32 Bit w/ 256 Megs Linear Address Space |
32 Bit w/ 4Gigs Linear Address Space |
|
Data Bus |
32 Bit |
32 Bit |
|
Registers |
16, 32bit user accessible registers |
16, 32 bit user accessible registers |
|
Cache |
4-KByte Direct-Mapped Instruction cache |
8K Unified 4-Way Set Associative Cache |
|
DMA |
2 Channel |
4 Channel |
|
DRAM |
Yes |
Yes |
|
UART |
2 Independent |
2 Duplex |
|
TIMER |
2 16 bit Timers |
2 16 bit Timers |
|
Debug Module |
Yes |
Yes |
|
Multiply-Accumulate Unit |
Yes |
Yes |
|
Hardware Divide Module |
Yes |
Yes |
|
SRAM |
8-KByte On-Chip SRAM |
4 Kbytes SRAM |
Figure 2:
Figure 3:
Figure 4:
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