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10:00am-10:25am: Continental Breakfast
10:25am-10:30am: Welcome by Dean Bahram Nassersharif, URI College of Engineering, & the Wkshp. Organizers
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10:30am-11:30am: Session 1, Temperature, Power and Energy
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(Session Chair: David Kaeli, Northeastern University)
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Fast Transient Thermal Simulation Based on Linear System Theory,
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Yongkui Han, Israel Koren and C. Mani Krishnaa, UMass, Amherst
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Impact of Process Variations on Low Power Cache Design,
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Mahmoud Bennaser and Csaba Andras Moritz, UMass, Amherst
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Compiler-Based Adaptive Fetch Throttling for Energy Efficiency,
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Huaping Wang, Yao Guo, Israel Koren and C. Mani Krishna, UMass, Amherst
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Energy-Aware Microprocessor Synchronization: Transactional Memory vs. Locks,
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Tali Moreshet, R. Iris Bahar and Maurice Herlihy, Brown University
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11:30am-11:45am: Short Break
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11:45am-12:45pm: Session 2, Architectures and Performance
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(Session Chair: C. Andras Moritz, University of Massachusetts, Amherst)
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Investigating the Effects of Wrong-Path Memory References in Shared-Memory Multiprocessor Systems,
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Ayse Yilmazer, URI; Resit Sendag, URI; Joshua J. Yi, Freescale Semiconductor; and Augustus K. Uht, URI
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Using R-STAGE to Optimize the DASAT Cache System,
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M. Tyler Maxwell, Charles C. Weems, J. Eliot B. Moss and Robert B. Moll, UMass, Amherst
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Exploring Architectural Challenges in Scalable Underwater Wireless Sensor Networks,
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Z. Jerry Shi and Yunsi Fei, University of Connecticut
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ILP is Dead, Long Live IPC!,
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Gus Uht, URI
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12:45pm-1:30pm: Sandwich Buffet Lunch
1:30pm-2:30pm: Keypanel Session, 'Whence Goeth the Microprocessor?' (Moderator: Gus Uht)
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Constituencies and Keypanelists:
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* Academia: Prof. Anant Agarwal, Professor of Electrical
Engineering and Computer Science, MIT.
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* End Users: Dr. Atul Chhabra, Enterprise Architect and
Senior IT Manager, Verizon, Inc.
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* Industry: Dr. Joel Emer, Fellow, Intel Corp.
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* Everybody: The Audience, various positions, many institutions.
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2:30pm-3:00pm: Long Break
3:00pm-4:00pm: Session 3, Simulation and Design
(Session Chair: Qing Yang, University of Rhode Island)
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Branch Trace Compression for Snapshot-Based Simulation,
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Kenneth C. Barr and Krste Asanovic, MIT
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Requirements for any HPC/FPGA Application Development Tool Flow
(that gets more than a small fraction of potential performance),
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Martin Herbordt, Tom VanCourt and Yongfeng Gu, Boston University
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Accelerating Architectural Exploration Using Canonical Instruction Segments,
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Rose F. Liu and Krste Asanovic, MIT
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Tortola: Addressing Tomorrow's Computing Challenges through Hardware/Software Symbiosis,
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Kim Hazelwood, University of Virginia and Intel Massachusetts
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4:00pm-4:15pm: Short Break
4:15pm-5:15pm: Session 4, Dependability (Session Chair: R. Iris Bahar, Brown University)
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PRINS: Optimizing Performance of Reliable Internet Storages,
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Weijun Xiao, Jin Ren and Qing Yang, URI
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Failure Detection in Programmable Network Processors,
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Yizheng Zhou, Vijay Lakamraju, Israel Koren and C.M. Krishna, UMass, Amherst
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Software Fault Detection Using Dynamic Instrumentation
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George A. Reis and David I. August, Princeton University; and
Robert Cohn and Shubhendu S. Mukherjee, Intel Massachusetts
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Self-healing Nanoscale Architectures on 2-D Nano-fabrics
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Teng Wang, Mahmoud Ben Naser, Yao Guo and Csaba Andras Moritz, UMass, Amherst
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5:15pm-5:45pm: Long Break
5:45pm-6:30pm: Session 5, Emerging Concepts
(Session Chair: Martin Herbordt, Boston University)
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Functional Programming in Embedded System Design,
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Al Strelzoff, E-TrolZ, Inc.
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The Fresh Breeze Memory Hierarchy,
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Jack B. Dennis, MIT
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Ideal and Resistive Nanowire Decoders: General Models for Nanowire Addressing,
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Eric Rachlin and John E. Savage, Brown University
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6:30pm-6:35pm: Closing Remarks
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