Static   D-type   Flip-Flop   II   Simulaition

Schematic Simulation Result
Q:
  • td (l->h) => 6.090 nSec
  • td (h->l) => 4.708 nSec
  • tr => 5.678 nSec
  • tf => 4.252 nSec
Q-:
  • td (l->h) => 5.697 nSec
  • td (h->l) => 7.116 nSec
  • tr => 1.134 nSec
  • tf => 1.409 nSec
Signal Rules:
  • Minimum CLK pulse width =4.58 nSec
  • Minimum time from D change to down-edge of CLK =3.191 nSec

                                                                        Simulation #1


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This web site is originally created by Sangmok Lee, July 7, 1998.