4-input NAND Simulation

4-input N A N D

Schematic Simulation Result

td (l->h) => 1.885 nSec
td (h->l) => 14.16 nSec
tr => 5.983 nSec
tf => 19.94 nSec

Simulation #1

Schematic Simulation Result

Output Result

\ In2,In3

00 01 10 11

In0,
In1 00 1 1 1 1

01 1 1 1 1

10 1 1 1 1

11 1 1 1 0

Simulation #2


td (l->h) => 1.885 nSec td (h->l) => 14.16 nSec tr => 5.983 nSec tf => 19.94 nSec