Static   D-type   Flip-Flop   (8/4, 8/4)   Simulaition

Schematic Simulation Result
Q:
  • td (l->h) => 11.070 nSec
  • td (h->l) => 4.1600 nSec
  • tr => 14.566 nSec
  • tf => 2.8150 nSec
Q-:
  • td (l->h) => 5.026 nSec
  • td (h->l) => 10.973 nSec
  • tr => 1.341 nSec
  • tf => 2.318 nSec
Signal Rules:
  • Minimum CLK pulse width = 7.042 nSec
  • Minimum distance between pluses = 11.180nSec
  • Minimum time from D change to down-edge of CLK = 6.715 nSec

                                                                        Simulation #1


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This web site is originally created by Sangmok Lee, July 7, 1998.