Static   D-type   Flip-Flop   II   (8/4, 8/4)   Simulaition

Schematic Simulation Result
Q:
  • td (l->h) => 6.152 nSec
  • td (h->l) => 4.220 nSec
  • tr => 6.006 nSec
  • tf => 3.460 nSec
Q-:
  • td (l->h) => 5.270 nSec
  • td (h->l) => 6.738 nSec
  • tr => 1.690 nSec
  • tf => 1.357 nSec
Signal Rules:
  • Minimum CLK pulse width =3.781 nSec
  • Minimum time from D change to down-edge of CLK =2.361 nSec

                                                                        Simulation #1


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This web site is originally created by Sangmok Lee, July 7, 1998.