Static   D-type   Flip-Flop   Simulaition

Schematic Simulation Result
Q:
  • td (l->h) => 7.277 nSec
  • td (h->l) => 4.483 nSec
  • tr => 9.446 nSec
  • tf => 3.345 nSec
Q-:
  • td (l->h) => 5.197 nSec
  • td (h->l) => 8.245 nSec
  • tr => 1.457 nSec
  • tf => 1.600 nSec
Signal Rules:
  • Minimum CLK pulse width = 15 nSec
  • Minimum time from D change to down-edge of CLK = 13.85 nSec

                                                                        Simulation #1


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This web site is originally created by Sangmok Lee, July 7, 1998.