NAND Simulation

N A N D

Schematic Simulation Result

td (l->h) => 2.0050 nSec
td (h->l) => 3.9160 nSec
tr => 4.1373 nSec
tf => 5.4420 nSec

Maximum delay Simulation #1

Schematic Simulation Result

td (l->h) => 2.2973 nSec
td (h->l) => 2.2560 nSec
tr => 3.851 nSec
tf => 3.633 nSec

Maximum Delay Simulation #2

Schematic Simulation Result

Function Table

A B OUT

0 0 1

0 1 1

1 0 1

1 1 0

Function Simulation


td (l->h) => 2.0050 nSec td (h->l) => 3.9160 nSec tr => 4.1373 nSec tf => 5.4420 nSec


td (l->h) => 2.2973 nSec td (h->l) => 2.2560 nSec tr => 3.851 nSec tf => 3.633 nSec