Selected publications of Augustus K. Uht

Selected publications and talks of Augustus K. Uht

Legal notice: Please respect the copyrights of the authors and publishers of the papers listed below.

PATENT'2013:: A. K. Uht, D. Morano, and D. Kaeli, "Not-taken path instruction for selectively generating a forwarded result from a previous instruction based on branch outcome ," USA Patent No. 8,601,245. Issued: December 3, 2013.

PATENT'2011:: A. K. Uht, D. Morano, and D. Kaeli, "Concurrent execution of instructions in a processing system," USA Patent No. 7,991,980. Issued: August 2, 2011.

PATENT'2010-2:: A. K. Uht, "System und verfahren zur leistungsverbesserung digitaler systeme," Germany Patent No. 60334837. Issued: December 16, 2010.

PATENT'2010:: R. Sendag, A. Yilmazer, and A. K. Uht, "System and method for cache replacement," USA Patent No. 7,721,048. Issued: May 18, 2010.

PATENT'2009:: A. K. Uht, "System and Method of Digital System Performance Enhancement," USA Patent No. 7,555,084. Issued: June 30, 2009.

GLSVLSI'2009:: M. Kadin, S. Reda, and A. K. Uht, "Central vs. distributed dynamic thermal management for multi-core processors: which one is better?," in Proceedings of the 19th ACM Great Lakes Symposium on VLSI. Boston, MA, USA: ACM, May 10-12, 2009, pp. 137-140.

PATENT'2008-2:: A. K. Uht, D. Morano, and D. Kaeli, "Automatic and Transparent Hardware Conversion of Traditional Control Flow to Predicates," USA Patent No. 7,409,534. Issued: August 5, 2008.

PATENT'2008-1:: A. K. Uht, D. Morano, and D. Kaeli, "Automatic and transparent hardware conversion of traditional control flow to predicates," USA Patent No. 7,380,108. Issued: May 27, 2008.

JPDC'2007:: R. Sendag, A. Yilmazer, J. Yi, and A. K. Uht, "The Impact of Wrong-Path Memory References in Cache-Coherent Multiprocessor Systems," Journal of Parallel and Distributed Computing, vol. 67 (2007), pp. 1256--1269, March 24 2007. Special Issue on Best Papers in 2006 IEEE International Parallel and Distributed Processing Symposium.

PATENT'2007:: A. K. Uht, D. Morano, and D. Kaeli, "Automatic and Transparent Hardware Conversion of Traditional Control Flow to Predicates," USA Patent No. 7,210,025. Issued: April 24, 2007.

IPDPS'2006:: R. Sendag, A. Yilmazer, J. Yi, and A. K. Uht, "Quantifying and Reducing the Effects of Wrong-Path Memory References in Cache-Coherent Multiprocessor Systems," in Proceedings of the 20th IEEE International Parallel & Distributed Processing Symposium (IPDPS 2006). Rhodes Island, Greece: IEEE, April 25-29, 2006. One of four Best Papers out of 531 submissions.

(WARFP'2006):: A. K. Uht, "TEAtime Adaptive-Computing Case-Study, Demonstration and Updated Results," 2nd Workshop on Architecture Research using FPGA Platforms (WARFP-2006), held in conjunction with the 12th International Symposium on High-Performance Computer Architecture (HPCA-12). Austin, Texas, USA, February 12, 2006. Accepted, was to appear; withdrawn due to illness.

BARC'2006-1:: A. K. Uht, "ILP is Dead, Long Live IPC!," in Proceedings of the Fourth Boston-Area Architecture Workshop (BARC 2006). Kingston, RI, USA, February 3, 2006. - Talk

BARC'2006-2:: A. Yilmazer, R. Sendag, J. Yi, and A. K. Uht, "Investigating the Effects of Wrong-Path Memory References in Shared-Memory Multiprocessor Systems," in Proceedings of the Fourth Boston-Area Architecture Workshop (BARC 2006). Kingston, RI, USA, February 3, 2006.

PATENT'2006:: A. K. Uht, "System and Method of Digital System Performance Enhancement," USA Patent No. 6,985,547. Issued: January 10, 2006.

PATENT'2005:: A. K. Uht, D. Morano, and D. Kaeli, "Resource Flow Computing Device," USA Patent No. 6,976,150. Issued: December 13, 2005.

TACS'2005:: A. K. Uht and R. J. Vaccaro, "TEAPC: Temperature Adaptive Computing in a Real PC," in Proceedings of the Second Workshop on Temperature-Aware Computer Systems (TACS-2), ISCA. Madison, WI, USA: IEEE and ACM, June 5, 2005. - Talk (14 MB) -

CRCPress'2005-2:: D. A. Morano, D. R. Kaeli, and A. K. Uht, "Resource Flow Microarchitectures," in Speculative Execution in High Performance Computer Architectures, D. Kaeli and P.-C. Yew, Eds. Boca Raton, FL, USA: CRC Press, May 2005, pp. 393-419.

CRCPress'2005:: A. K. Uht, "Multipath Execution," in Speculative Execution in High Performance Computer Architectures, D. Kaeli and P.-C. Yew, Eds. Boca Raton, FL, USA: CRC Press, May 2005, pp. 135-160.

IEEETC'2005:: A. K. Uht, "Uniprocessor Performance Enhancement through Adaptive Clock Frequency Control," IEEE Transactions on Computers, vol. 54, no. 2, pp. 132-140, February 2005.

BARC'2005:: A. K. Uht and R. J. Vaccaro, "Adaptive Computing," in Proceedings of the Third Annual Boston Architecture Conference (BARC-2005). Brown University, Providence, RI, USA, January 21 2005. - Published Talk - Actual Talk - Extended abstract -

PATDOC'2004:: A. K. Uht, "System and Method of Digital System Performance Enhancement," World (non-USA) patent source document, October 28, 2004.

IBM-PAC2'2004:: A. K. Uht and R. J. Vaccaro, "TEAPC: Adaptive Computing and Underclocking in a Real PC," in Proceedings of the First IBM P=ac2 Conference. Yorktown Heights, NY, USA: IBM T.J. Watson Research Center, October 6-8, 2004, pp. 45-54. - Talk - Extended paper (TR) -

Computer'2004:: A. K. Uht, "Going Beyond Worst-Case Specs with TEAtime," Computer, March 2004, special issue on 'Better Than Worst-Case Design.' - Related Talk -

SSCCII'2004:: A. K. Uht, "Teradactyl: an Easy-to-Use Supercomputer," in Proceedings of the International Symposium of Santa Caterina on Challenges in the Internet and Interdisciplinary Research (SSCCII-2004). Amalfi, Italy: IPSI, January-February 2004. - Talk -

JILP'2003:: A. K. Uht, D. Morano, A. Khalafi, and D. R. Kaeli, "Levo - A Scalable Processor With High IPC," The Journal of Instruction-Level Parallelism, vol. 5, August 2003 (http://www.jilp.org/vol5 ). - Related Talk -

SSGRRw'2003:: A. K. Uht, "Uniprocessor Performance Enhancement Through Adaptive Clock Frequency Control," in Proceedings of the SSGRR-2003w International Conference on Advances in Infrastructure for e-Business, e-Education, e-Science, e-Medicine, and Mobile Technologies on the Internet. L'Aquila, Italy: Telecom Italia, January 6-12, 2003. Invited paper.

NEU-TR'2002:: D. Morano, A. Khalafi, D. R. Kaeli, and A. K. Uht, "Implications of Register and Memory Temporal Locality for Distributed Microarchitectures," Dept. of Electrical and Computer Engineering, Northeastern University, Boston, MA, USA, Technical Report, October 2002.

MEDEA2002:: D. Morano, A. Khalafi, D. R. Kaeli, and A. K. Uht, "Realizing High IPC Through a Scalable Memory-Latency Tolerant Multipath Microarchitecture," in Proceedings of the Workshop On Chip Multiprocessors: Processor Architecture and Memory Hierarchy Related Issues (MEDEA2002), at PACT 2002. Charlottesville, Virginia, USA, September 22, 2002. ACM SIGARCH Computer Architecture Newsletter, March 2003.

URI-ELE-TR'2002-5:: A. K. Uht, D. Morano, A. Khalafi, and D. Kaeli, "Levo - A Scalable Billion Transistor CPU With High IPC," Dept. of Electrical and Computer Engineering, University of Rhode Island, Kingston, RI 02881-0805, Technical Report 082002-1000, August 2002.

Euro-Par2002:: A. Uht, A. Khalafi, D. Morano, M. d. Alba, and D. Kaeli, "Realizing High IPC Using Time-Tagged Resource Flow Computing," in Proceedings of the Euro-Par 2002 Conference, Springer-Verlag Lecture Notes in Computer Science. Paderborn, Germany: ACM, IFIP, August 28, 2002, pp. 490-499. - Talk -

URI-ELE-TR'2002-4:: A. Khalafi, D. A. Morano, D. R. Kaeli, and A. K. Uht, "Multipath Execution on a Large-Scale Distributed Microarchitecture," Department of Electrical and Computer Engineering, University of Rhode Island, Kingston, RI 02881-0805, Technical Report 032002-0103, February 15, 2002.

URI-ELE-TR'2002-3:: A. Khalafi, D. A. Morano, D. R. Kaeli, and A. K. Uht, "Realizing High IPC Through a Scalable Memory-Latency Tolerant Multipath Microarchitecture," Department of Electrical and Computer Engineering, University of Rhode Island, Kingston, RI 02881-0805, Technical Report 032002-0101, April 2, 2002.

SIGARCH-CAN'2002:: A. K. Uht, "Disjoint Eager Execution: What It Is / What It Is Not," ACM SIGARCH Computer Architecture News, vol. 30, no. 1, March 2002.

URI-ELE-TR'2002-2:: D. Morano, "Execution-Time Instruction Predication," Dept. of Electrical and Computer Engineering, University of Rhode Island, Kingston, RI 02881, Technical Report 032002-0100, March 2002.

SSGRRw'2002:: A. K. Uht, S. Langford, and D. Morano, "Interactive High-Performance Processor Understanding via the Web," in Proceedings of the SSGRR 2002w International Conference on Advances in Infrastructure for e-Business, e-Education, e-Science, and e-Medicine on the Internet. L'Aquila, Italy, January 21-27, 2002. LevoVis paper. - Talk -

URI-ELE-TR'2002:: D. Morano, D. R. Kaeli, and A. K. Uht, "Preserving Dependencies in a Large-Scale Distributed Microarchitecture," Dept. of Electrical and Computer Engineering, University of Rhode Island, Kingston, RI 02864, Technical 022002-001, December 21, 2001.

PACT-WIP'2001:: A. K. Uht, A. Khalafi, D. Morano, T. Wenisch, M. de Alba, and D. Kaeli, "Levo: IPC in the 10's via Resource Flow Computing," IEEE TCCA Newsletter, Special Issue, December 2001. Presented at PACT 2001 Work-In-Progress (WIP) Session, September 2001. - PDF (213 KB) -

URI-ELE-TR'2001-2:: A. K. Uht, D. Morano, A. Khalafi, M. de Alba, T. Wenisch, M. Ashouei, and D. Kaeli, "IPC in the 10's via Resource Flow Computing with Levo," Department of Electrical and Computer Engineering, University of Rhode Island, Kingston, RI, Technical 092001-001, September 18, 2001. - PDF (328 KB) -

URI-ELE-TR'2001:: T. Wenisch and A. K. Uht, "HDLevo - VHDL Modeling of Levo Processor Components," Department of Electrical and Computer Engineering, University of Rhode Island, Kingston, RI, Technical Report 072001-100, July 20, 2001. - PDF (332 KB) -

ISIT2001:: T. Wenisch, P. F. Swaszek and A. K. Uht. "Combined Error Correcting and Compressing Codes".; 2001 IEEE International Symposium on Information Theory, to appear June, 2001.; - PDF (100 KB) / No Abstract / PDF Extended Summary - not published (131 KB) -

IEEEMicro2000:: A. K. Uht, J.-C. Lo, J. C. Daly, Y. Sun and J. Kowalski. "Building Real Computer Systems".; IEEE Micro, Special Issue on Computer Architecture Education, Vol. 20, No. 3, May/June, 2000. pp. 48-56.; - PDF (657 KB) / No Abstract -

ASEE2000:: A. K. Uht. "The URI Integrated Computer Engineering Design (ICED) Curriculum: Progress Report".; 2000 ASEE Conference & Exposition, June, 2000. 7 pages.; - PDF (353 KB) / No Abstract -

URI-ELE-TR'2000:: A. K. Uht. "Acheiving Typical Delays in Synchronous Systems via Timing Error Toleration." Technical Report No. 032000-0100. Dept. of Electrical and Computer Engineering, University of Rhode Island, March 10, 2000. - Abstract -

TCCA'99:: A. K. Uht. "The Integrated Computer Engineering Design (ICED) Curriculum".; IEEE Technical Committee on Computer Architecture Newsletter, Special Issue on Computer Architecture Education.; IEEE, February, 1999. 3 pages.; - Compressed Postscript (33 KB) / No Abstract / Uncompressed Postscript (83 KB) -

FIE'98:: A. K. Uht and Y. Sun. "The Laboratory Environment of the URI Integrated Computer Engineering Design (ICED) Curriculum".; 1998 Frontiers in Education Conference, ASEE and IEEE, November, 1998. 6 pages.; - PDF (995 KB) / Compressed Postscript (782 KB) / No Abstract / Uncompressed Postscript (1.95 MB) -
WCAE'98 (ISCA):: A. K. Uht. "The Integrated Computer Engineering Design (ICED) Curriculum".; Proceedings of the 1998 Workshop on Computer Architecture Education.; Held at the 25th International Symposium on Computer Architecture, Barcelona, June 1998. 6 pages.; - Compressed Postscript (57 KB) / No Abstract / Uncompressed Postscript (142 KB) -
WCAE'98 (HPCA):: A. K. Uht. "The Integrated Computer Engineering Design (ICED) Curriculum".; Proceedings of the 4th Workshop on Computer Architecture Education.; Held at the 4th High Performance Computer Architecture Conference, Las Vegas, January 1998. 9 pages.; - Compressed Postscript (39 KB) / No Abstract / Uncompressed Postscript (99 KB) -
MUG'97:: A. K. Uht. "Use of CAD Tools in the Integrated Computer Engineering Design (ICED) Curriculum".; Proceedings of the 14th International Conference of the Mentor Graphics Users' Group.; International Mentor Graphics Users' Group, October, 1997. 6 pages.; - Compressed Postscript (58 KB) / Abstract / Uncompressed Postscript (138 KB) -
URI-ELE-TR'97-4:: A. K. Uht. "High Performance Memory System for High ILP Microarchitectures".; Technical Report No. 0797-0002. Dept. of Electrical and Computer Engineering,; University of Rhode Island, August 26, 1997.; - Compressed Postscript (81 KB) / No Abstract / Uncompressed Postscript (208 KB) -
URI-ELE-TR'97-2-A:: A. K. Uht. "Verification of ILP Speedups in the 10's for Disjoint Eager Execution".; Technical Report No. 0697-0001, Rev. A. Dept. of Electrical and Computer Engineering,; University of Rhode Island, July 11, 1997.; - Compressed Postscript (390 KB) / Abstract / Uncompressed Postscript (1190 KB) -
COMPUTER'97:: A. K. Uht, V. Sindagi and S. Somanathan. "Branch Effect Reduction Techniques".; COMPUTER, IEEE, 30(5):71-81, May, 1997. Originally entitled: "Reducing the Ill Effects of Branches".; - PDF (375 KB) / Abstract / No Postscript -
URI-ELE-TR'97:: A. K. Uht, V. Sindagi and S. Somanathan. "Data References for: `Branch Effect Reduction Techniques'".; Technical Report No. 0497-0002. Dept. of Electrical and Computer Engineering,; University of Rhode Island, April 25, 1997.; - Compressed Postscript (57 KB) / No Abstract / Uncompressed Postscript (139 KB) -
MICRO'95:: A. K. Uht and V. Sindagi. "Disjoint Eager Execution: An Optimal Form of Speculative Execution".; In Proceedings of the 28th International Symposium on Microarchitecture (MICRO-28).; ACM-IEEE, November/December 1995, pages 313-325.; - Abstract / Talk -; |- Disjoint Eager Execution Tutorial -|
PATENT'93:: A. K. Uht, "System for Extracting Low-Level Concurrency from Serial Instruction Streams," USA Patent No. 5,201,057. Issued: April 6, 1993.
SIGARCH CAN'93:: A. K. Uht. "Extraction of Massive Instruction Level Parallelism".; ACM SIGARCH Computer Architecture News, 21(2 and 3), March and June 1993.; - Compressed Postscript (55KB) / Abstract / Uncompressed Postscript (192KB) -
MICRO'92:: A. K. Uht and D. B. Johnson. "Data Path Issues in a Highly Concurrent Machine."; In Proceedings of the Twenty-Fifth International Symposium on Microarchitecture (MICRO-25),; pages 115-118. ACM-IEEE, December 1992.; - No Compressed Postscript / No Abstract / Uncompressed Postscript (79KB) -
IEEETPDS'92:: A. K. Uht. "Requirements for Optimal Execution of Loops with Tests".; IEEE Transactions on Parallel and Distributed Systems, 3(5):573-581, September 1992.
UCSD-CSE-TR'92:: A. K. Uht and D. B. Johnson. "Data Path Issues in a Highly Concurrent Machine". Technical Report CS92-262,; Department of Computer Science and Engineering, University of California, San Diego, September 1992.
IEEETC'92:: A. K. Uht. "Concurrency Extraction via Hardware Methods Executing the Static Instruction Stream".; IEEE Transactions on Computers, 41(7):826-841, July 1992.
ISCA'92:: A. K. Uht and D. B. Johnson. "Data Path Issues in a Highly Concurrent Machine".; In Proceedings of the 19th International Symposium on Computer Architecture, page 431.; ACM-IEEE, May 1992. Abstract. Poster presented at conference.
IEEETC'91:: A. K. Uht. "A Theory of Reduced and Minimal Procedural Dependencies".; IEEE Transactions on Computers, 40(6):681-692, June 1991.; - Also appears in the tutorial Instruction-Level Parallel Processors, Torng, H.C. and Vassiliadis, S., Eds.,; IEEE Computer Society Press, 1995, pages 171-182.
UCSD-CSE-TR'90:: A. K. Uht. "Notes on: 'A Theory of Reduced and Minimal Procedural Dependencies'".; Dept. of Computer Science and Engineering, UCSD, 1990.; - No Compressed Postscript / No Abstract / Uncompressed Postscript (69KB) -
UCSD-CSE-TR'90-2:: A. K. Uht and S. Wang. "Understanding Eager Evaluation of Imperative Instruction Streams, Part 1"; Dept. of Computer Science and Engineering, UCSD, June, 1990.; - No Compressed Postscript / No Abstract / Uncompressed Postscript (95KB) -
WPLCPC'89:: A. K. Uht. "Desirable Code Transformations for a Concurrent Machine".; In Languages and Compilers for Parallel Computing, Research Monographs in Parallel and Distributed Computing.; The MIT Press, 1990.
ICS'88: A. K. Uht. "Requirement for Optimal Execution of Loops with Tests". In Proceedings of the the 1988 ACM International Conference on Supercomputing, St. Malo, France, June 1988.
MICRO'87: A. K. Uht, C. Polychronopoulos and J. F. Kolen. "On the Combination of Hardware and Software Concurrency Extraction Methods". In Proceedings of the the 1987 Workshop on Microprogramming, ACM, Colorado, 1987.

Archived - Superseded Documents

URI-ELE-TR'97-3:: A. K. Uht. "Overview of the Levo High-ILP Computer". Technical Report No. 0797-0001.; Dept. of Electrical and Computer Engineering, University of Rhode Island, August 26, 1997.; - Compressed Postscript (770 KB) / No Abstract / Uncompressed Postscript (2444 KB) -
URI-ELE-TR'97-2:: A. K. Uht. "Verification of ILP Speedups in the 10's for Disjoint Eager Execution". Technical Report No. 0697-0001.; Dept. of Electrical and Computer Engineering, University of Rhode Island, June 24, 1997.; - Compressed Postscript (382 KB) / Abstract / Uncompressed Postscript (1168 KB) -
COMPUTER'96:: A. K. Uht, V. Sindagi and S. Somanathan. "Reducing the Ill Effects of Branches".; IEEE COMPUTER, to appear, 1996.; - Compressed Postscript (91KB) / Abstract / Uncompressed Postscript (258KB) -
URI-ELE-TR'96:: A. K. Uht, V. Sindagi and S. Somanathan. "Data References for: `Reducing the Ill Effects of Branches'".; Technical Report No. 0496-0001. Dept. of Electrical and Computer Engineering, University of Rhode Island, April 3, 1996.; - Compressed Postscript (50KB) / No Abstract / Uncompressed Postscript (119KB) -

hits since June 7, 1996.

June 6, 2017 | Gus Uht | uht@ele.uri.edu