ELE 343 LAB 7
JFET Amplifier


Figure 1   JFET gate controls drain current by creating a depletion region. The depletion region increases when the gate voltage becomes more negative.


Figure 2   One transistor JFET amplifier.

In this lab we design, simulate and test a one transistor FET amplifier. The transistor used is the 2N5459 JFET. JFETs are junction field effect transistors. They are formed by an n-type diffusion in a p-type region. The structure is shown in Figure 1. At the junction, electrons and holes recombine, forming a region depleted of carriers. This depletion region increases in size when the reverse bias on the junction increases. When the depletion region extends completely across the p-type region the transistor is cut off. This occurs at a negative gate to source voltage. Therefore the transistor threshold voltage is negative. As the gate becomes more positive, the depletion region decreases and more drain current flows. If the gate to source voltage exceeds about 0.6V, the pn junction becomes forward biased enough for gate current to flow. In normal operation, the gate junction is reversed biased. Only a small leakage current flows in the gate.

Transistor Properties

The SPICE model for the JFET uses the MOSFET equations.

ID = K(Vgs - VTR)2(1 + LAMBDA*VDS)

for VDS > Vgs - VTR

and
ID = K[2(Vgs - VTR)VDS - VDS2]

for VDS < Vgs - VTR

For the jfet model, SPICE uses the parameter BETA for K. BETA = K.

Model Parameters

The data sheet under off characteristic shows a typical gate to source voltage of -4.5V. This is the threshold voltage.

The data sheet on characteristics show a drain current of 9 mA when Vgs is zero. Since

ID = K(Vgs - VTR)2
If, Vgs = 0, and ID = 9 mA, K = 4.4x10-4

The data sheet also gives gm between 4000 and 6000 umhos
Taking the average gm = 4000x10-6 = 4x10-3 (Transfer Admittance Common Source).
And
1/ro = 10 umhos (Output Admittance).
ro = 100K

SPICE Model

The following is a SPICE model based on the values in the data sheet. 


	.model JbreakN-X NJF BETA = 4.4E-4  VTO = -4.5  LAMBDA = 1E-3
Using the 'schematics' program, place the part JBREAKN. This is a JFET with no model. Then select the jfet on the schematic and select Edit Model in the edit pull down menu. Then select 'EDIT MODEL INSTANCE (TEXT). In the window that comes up, type in the model parameter values. This is the same proceedure that's described in the tutorial PSPICE Model Editing.

In This Lab

  1. Design an amplifier using the circuit configuration shown in Figure 2.

  2. Simulate the bias point and the small signal gain. Sweep the frequency over an appropriate range.

  3. Build the amplifier and verify performance.
Questions

  1. Explain any discrepancies between the simulation and measurement.