Modified and corrected from Tom
Dickens. Please notify me of any
errors!
Mnemonic |
Operation |
Addressing
|
Instruction |
Bytes |
Cycles |
Condition Codes |
||
Prebyte |
Opcode |
Operand |
|
|||||
ABA |
Add Accumulators |
INH |
— |
1B |
— |
1 |
2 |
|
ABX |
Add B to X |
INH |
— |
3A |
— |
1 |
3 |
|
ABY |
Add B to Y |
INH |
18 |
3A |
— |
2 |
4 |
|
ADCA |
Add with Carry to A |
IMM |
— |
89 |
ii |
2 |
2 |
|
DIR |
— |
99 |
dd |
2 |
3 |
|||
EXT |
— |
B9 |
hh ll |
3 |
4 |
|||
IND, X |
— |
A9 |
ff |
2 |
4 |
|||
IND, Y |
18 |
A9 |
ff |
3 |
5 |
|||
ADCB |
Add with Carry to B |
IMM |
— |
C9 |
ii |
2 |
2 |
|
DIR |
— |
D9 |
dd |
2 |
3 |
|||
EXT |
— |
F9 |
hh ll |
3 |
4 |
|||
IND, X |
— |
E9 |
ff |
2 |
4 |
|||
IND, Y |
18 |
E9 |
ff |
3 |
5 |
|||
ADDA |
Add Memory to A |
IMM |
— |
8B |
ii |
2 |
2 |
|
DIR |
— |
9B |
dd |
2 |
3 |
|||
EXT |
— |
BB |
hh ll |
3 |
4 |
|||
IND, X |
— |
AB |
ff |
2 |
4 |
|||
IND, Y |
18 |
AB |
ff |
3 |
5 |
|||
ADDB |
Add Memory to B |
IMM |
— |
CB |
ii |
2 |
2 |
|
DIR |
— |
DB |
dd |
2 |
3 |
|||
EXT |
— |
FB |
hh ll |
3 |
4 |
|||
IND, X |
— |
EB |
ff |
2 |
4 |
|||
IND, Y |
18 |
EB |
ff |
3 |
5 |
|||
ADDD |
Add 16-Bit to D |
IMM |
— |
C3 |
jj kk |
3 |
4 |
|
DIR |
— |
D3 |
dd |
2 |
5 |
|||
EXT |
— |
F3 |
hh ll |
3 |
6 |
|||
IND, X |
— |
E3 |
ff |
2 |
6 |
|||
IND, Y |
18 |
E3 |
ff |
3 |
7 |
|||
ANDA |
AND A with Memory |
IMM |
— |
84 |
ii |
2 |
2 |
|
DIR |
— |
94 |
dd |
2 |
3 |
|||
EXT |
— |
B4 |
hh ll |
3 |
4 |
|||
IND, X |
— |
A4 |
ff |
2 |
4 |
|||
IND, Y |
18 |
A4 |
ff |
3 |
5 |
|||
ANDB |
AND B with Memory |
IMM |
— |
C4 |
ii |
2 |
2 |
|
DIR |
— |
D4 |
dd |
2 |
3 |
|||
EXT |
— |
F4 |
hh ll |
3 |
4 |
|||
IND, X |
— |
E4 |
ff |
2 |
4 |
|||
IND, Y |
18 |
E4 |
ff |
3 |
5 |
|||
ASL |
Arithmetic Shift Left |
EXT |
— |
78 |
hh ll |
3 |
6 |
|
IND, X |
— |
68 |
ff |
2 |
6 |
|||
IND, Y |
18 |
68 |
ff |
3 |
7 |
|||
ASLA |
Arithmetic Shift Left A |
INH |
— |
48 |
— |
1 |
2 |
|
ASLB |
Arithmetic Shift Left B |
INH |
— |
58 |
— |
1 |
2 |
|
ASLD |
Arithmetic Shift Left D |
INH |
— |
05 |
— |
1 |
3 |
|
ASR |
Arithmetic Shift Right |
EXT |
— |
77 |
hh ll |
3 |
6 |
|
IND, X |
— |
67 |
ff |
2 |
6 |
|||
IND, Y |
18 |
67 |
ff |
3 |
7 |
|||
ASRA |
Arithmetic Shift Right A |
INH |
— |
47 |
— |
1 |
2 |
|
ASRB |
Arithmetic Shift Right B |
INH |
— |
57 |
— |
1 |
2 |
|
BCC |
Branch if Carry Clear |
REL |
— |
24 |
rr |
2 |
3 |
|
BCLR |
Clear Bit(s) |
DIR |
— |
15 |
dd mm |
3 |
6 |
|
IND, X |
— |
1D |
ff mm |
3 |
7 |
|||
IND, Y |
18 |
1D |
ff mm |
4 |
8 |
|||
BCS |
Branch if Carry Set |
REL |
— |
25 |
rr |
2 |
3 |
|
BEQ |
Branch if = Zero |
REL |
— |
27 |
rr |
2 |
3 |
|
BGE |
Branch if ≥ Zero |
REL |
— |
2C |
rr |
2 |
3 |
|
BGT |
Branch if > Zero |
REL |
— |
2E |
rr |
2 |
3 |
|
BHI |
Branch if Higher |
REL |
— |
22 |
rr |
2 |
3 |
|
BHS |
Branch if Higher or Same |
REL |
— |
24 |
rr |
2 |
3 |
|
BITA |
Bit(s) Test A with Memory |
IMM |
— |
85 |
ii |
2 |
2 |
|
DIR |
— |
95 |
dd |
2 |
3 |
|||
EXT |
— |
B5 |
hh ll |
3 |
4 |
|||
IND, X |
— |
A5 |
ff |
2 |
4 |
|||
IND, Y |
18 |
A5 |
ff |
3 |
5 |
|||
BITB |
Bit(s) Test B with Memory |
IMM |
— |
C5 |
ii |
2 |
2 |
|
DIR |
— |
D5 |
dd |
2 |
3 |
|||
EXT |
— |
F5 |
hh ll |
3 |
4 |
|||
IND, X |
— |
E5 |
ff |
2 |
4 |
|||
IND, Y |
18 |
E5 |
ff |
3 |
5 |
|||
BLE |
Branch if ≤ Zero |
REL |
— |
2F |
rr |
2 |
3 |
|
BLO |
Branch if Lower |
REL |
— |
25 |
rr |
2 |
3 |
|
BLS |
Branch if Lower or Same |
REL |
— |
23 |
rr |
2 |
3 |
|
BLT |
Branch if < Zero |
REL |
— |
2D |
rr |
2 |
3 |
|
BMI |
Branch if Minus |
REL |
— |
2B |
rr |
2 |
3 |
|
BNE |
Branch if Not = Zero |
REL |
— |
26 |
rr |
2 |
3 |
|
BPL |
Branch if Plus |
REL |
— |
2A |
rr |
2 |
3 |
|
BRA |
Branch Always |
REL |
— |
20 |
rr |
2 |
3 |
|
BRCLR |
Branch if Bit(s) Clear |
DIR |
— |
13 |
dd mm rr |
4 |
6 |
|
IND, X |
— |
1F |
ff mm rr |
4 |
7 |
|||
IND, Y |
18 |
1F |
ff mm rr |
5 |
8 |
|||
BRN |
Branch Never |
REL |
— |
21 |
rr |
2 |
3 |
|
BRSET |
Branch if Bit(s) Set |
DIR |
— |
12 |
dd mm rr |
4 |
6 |
|
IND, X |
— |
1E |
ff mm rr |
4 |
7 |
|||
IND, Y |
18 |
1E |
ff mm rr |
5 |
8 |
|||
BSET |
Set Bit(s) |
DIR |
— |
14 |
dd mm |
3 |
6 |
|
IND, X |
— |
1C |
ff mm |
3 |
7 |
|||
IND, Y |
18 |
1C |
ff mm |
4 |
8 |
|||
BSR |
Branch to Subroutine |
REL |
— |
8D |
rr |
2 |
6 |
|
BVC |
Branch if Overflow Clear |
REL |
— |
28 |
rr |
2 |
3 |
|
BVS |
Branch if Overflow Set |
REL |
— |
29 |
rr |
2 |
3 |
|
Mnemonic |
Operation |
Addressing
|
Instruction |
Bytes |
Cycles |
Condition Codes |
||
Prebyte |
Opcode |
Operand |
|
|||||
CBA |
Compare A to B |
INH |
— |
11 |
— |
1 |
2 |
|
CLC |
Clear Carry Bit |
INH |
— |
0C |
— |
1 |
2 |
|
CLI |
Clear Interrupt Mask |
INH |
— |
0E |
— |
1 |
2 |
|
CLR |
Clear Memory Byte |
EXT |
— |
7F |
hh ll |
3 |
6 |
|
IND, X |
— |
6F |
ff |
2 |
6 |
|||
IND, Y |
18 |
6F |
ff |
3 |
7 |
|||
CLRA |
Clear Accumulator A |
INH |
— |
4F |
— |
1 |
2 |
|
CLRB |
Clear Accumulator B |
INH |
— |
5F |
— |
1 |
2 |
|
CLV |
Clear Overflow Flag |
INH |
— |
0A |
— |
1 |
2 |
|
CMPA |
Compare A to Memory |
IMM |
— |
81 |
ii |
2 |
2 |
|
DIR |
— |
91 |
dd |
2 |
3 |
|||
EXT |
— |
B1 |
hh ll |
3 |
4 |
|||
IND, X |
— |
A1 |
ff |
2 |
4 |
|||
IND, Y |
18 |
A1 |
ff |
3 |
5 |
|||
CMPB |
Compare B to Memory |
IMM |
— |
C1 |
ii |
2 |
2 |
|
DIR |
— |
D1 |
dd |
2 |
3 |
|||
EXT |
— |
F1 |
hh ll |
3 |
4 |
|||
IND, X |
— |
E1 |
ff |
2 |
4 |
|||
IND, Y |
18 |
E1 |
ff |
3 |
5 |
|||
COM |
1's Complement Memory Byte |
EXT |
— |
73 |
hh ll |
3 |
6 |
|
IND, X |
— |
63 |
ff |
2 |
6 |
|||
IND, Y |
18 |
63 |
ff |
3 |
7 |
|||
COMA |
1's Complement A |
INH |
— |
43 |
— |
1 |
2 |
|
COMB |
1's Complement B |
INH |
— |
53 |
— |
1 |
2 |
|
CPD |
Compare D to Memory 16-Bit |
IMM |
1A |
83 |
jj kk |
4 |
5 |
|
DIR |
1A |
93 |
dd |
3 |
6 |
|||
EXT |
1A |
B3 |
hh ll |
4 |
7 |
|||
IND, X |
1A |
A3 |
ff |
3 |
7 |
|||
IND, Y |
CD |
A3 |
ff |
3 |
7 |
|||
CPX |
Compare X to Memory 16-Bit |
IMM |
— |
8C |
jj kk |
3 |
4 |
|
DIR |
— |
9C |
dd |
2 |
5 |
|||
EXT |
— |
BC |
hh ll |
3 |
6 |
|||
IND, X |
— |
AC |
ff |
2 |
6 |
|||
IND, Y |
CD |
AC |
ff |
3 |
7 |
|||
CPY |
Compare Y to Memory 16-Bit |
IMM |
18 |
8C |
jj kk |
4 |
5 |
|
DIR |
18 |
9C |
dd |
3 |
6 |
|||
EXT |
18 |
BC |
hh ll |
4 |
7 |
|||
IND, X |
1A |
AC |
ff |
3 |
7 |
|||
IND, Y |
18 |
AC |
ff |
3 |
7 |
|||
DAA |
Decimal Adjust A |
INH |
— |
19 |
— |
1 |
2 |
|
DEC |
Decrement Memory Byte |
EXT |
— |
7A |
hh ll |
3 |
6 |
|
IND, X |
— |
6A |
ff |
2 |
6 |
|||
IND, Y |
18 |
6A |
ff |
3 |
7 |
|||
DECA |
Decrement Accumulator A |
INH |
— |
4A |
— |
1 |
2 |
|
DECB |
Decrement Accumulator B |
INH |
— |
5A |
— |
1 |
2 |
|
DES |
Decrement Stack Pointer |
INH |
— |
34 |
— |
1 |
3 |
|
DEX |
Decrement Index Register X |
INH |
— |
09 |
— |
1 |
3 |
|
DEY |
Decrement Index Register Y |
INH |
18 |
09 |
— |
2 |
4 |
|
EORA |
Exclusive OR A with Memory |
IMM |
— |
88 |
ii |
2 |
2 |
|
DIR |
— |
98 |
dd |
2 |
3 |
|||
EXT |
— |
B8 |
hh ll |
3 |
4 |
|||
IND, X |
— |
A8 |
ff |
2 |
4 |
|||
IND, Y |
18 |
A8 |
ff |
3 |
5 |
|||
EORB |
Exclusive OR B with Memory |
IMM |
— |
C8 |
ii |
2 |
2 |
|
DIR |
— |
D8 |
dd |
2 |
3 |
|||
EXT |
— |
F8 |
hh ll |
3 |
4 |
|||
IND, X |
— |
E8 |
ff |
2 |
4 |
|||
IND, Y |
18 |
E8 |
ff |
3 |
5 |
|||
FDIV |
Fractional Divide 16 by 16 |
INH |
— |
03 |
— |
1 |
41 |
|
IDIV |
Integer Divide 16 by 16 |
INH |
— |
02 |
— |
1 |
41 |
|
INC |
Increment Memory Byte |
EXT |
— |
7C |
hh ll |
3 |
6 |
|
IND, X |
— |
6C |
ff |
2 |
6 |
|||
IND, Y |
18 |
6C |
ff |
3 |
7 |
|||
INCA |
Increment Accumulator A |
INH |
— |
4C |
— |
1 |
2 |
|
INCB |
Increment Accumulator B |
INH |
— |
5C |
— |
1 |
2 |
|
INS |
Increment Stack Pointer |
INH |
— |
31 |
— |
1 |
3 |
|
INX |
Increment Index Register X |
INH |
— |
08 |
— |
1 |
3 |
|
INY |
Increment Index Register Y |
INH |
18 |
08 |
— |
2 |
4 |
|
JMP |
Jump |
EXT |
— |
7E |
hh ll |
3 |
3 |
|
IND, X |
— |
6E |
ff |
2 |
3 |
|||
IND, Y |
18 |
6E |
ff |
3 |
4 |
|||
JSR |
Jump to Subroutine |
DIR |
— |
9D |
dd |
2 |
5 |
|
EXT |
— |
BD |
hh ll |
3 |
6 |
|||
IND, X |
— |
AD |
ff |
2 |
6 |
|||
IND, Y |
18 |
AD |
ff |
3 |
7 |
|||
Mnemonic |
Operation |
Addressing
|
Instruction |
Bytes |
Cycles |
Condition Codes |
||
Prebyte |
Opcode |
Operand |
|
|||||
LDAA |
Load Accumulator A |
IMM |
— |
86 |
ii |
2 |
2 |
|
DIR |
— |
96 |
dd |
2 |
3 |
|||
EXT |
— |
B6 |
hh ll |
3 |
4 |
|||
IND, X |
— |
A6 |
ff |
2 |
4 |
|||
IND, Y |
18 |
A6 |
ff |
3 |
5 |
|||
LDAB |
Load Accumulator B |
IMM |
— |
C6 |
ii |
2 |
2 |
|
DIR |
— |
D6 |
dd |
2 |
3 |
|||
EXT |
— |
F6 |
hh ll |
3 |
4 |
|||
IND, X |
— |
E6 |
ff |
2 |
4 |
|||
IND, Y |
18 |
E6 |
ff |
3 |
5 |
|||
LDD |
Load Double Accumulator D |
IMM |
— |
CC |
jj kk |
3 |
3 |
|
DIR |
— |
DC |
dd |
2 |
4 |
|||
EXT |
— |
FC |
hh ll |
3 |
5 |
|||
IND, X |
— |
EC |
ff |
2 |
5 |
|||
IND, Y |
18 |
EC |
ff |
3 |
6 |
|||
LDS |
Load Stack Pointer |
IMM |
— |
8E |
jj kk |
3 |
3 |
|
DIR |
— |
9E |
dd |
2 |
4 |
|||
EXT |
— |
BE |
hh ll |
3 |
5 |
|||
IND, X |
— |
AE |
ff |
2 |
5 |
|||
IND, Y |
18 |
AE |
ff |
3 |
6 |
|||
LDX |
Load Index Register X |
IMM |
— |
CE |
jj kk |
3 |
3 |
|
DIR |
— |
DE |
dd |
2 |
4 |
|||
EXT |
— |
FE |
hh ll |
3 |
5 |
|||
IND, X |
— |
EE |
ff |
2 |
5 |
|||
IND, Y |
CD |
EE |
ff |
3 |
6 |
|||
LDY |
Load Index Register Y |
IMM |
18 |
CE |
jj kk |
4 |
4 |
|
DIR |
18 |
DE |
dd |
3 |
5 |
|||
EXT |
18 |
FE |
hh ll |
4 |
6 |
|||
IND, X |
1A |
EE |
ff |
3 |
6 |
|||
IND, Y |
18 |
EE |
ff |
3 |
6 |
|||
LSL |
Logical Shift Left |
EXT |
— |
78 |
hh ll |
3 |
6 |
|
IND, X |
— |
68 |
ff |
2 |
6 |
|||
IND, Y |
18 |
68 |
ff |
3 |
7 |
|||
LSLA |
Logical Shift Left A |
INH |
— |
48 |
— |
1 |
2 |
|
LSLB |
Logical Shift Left B |
INH |
— |
58 |
— |
1 |
2 |
|
LSLD |
Logical Shift Left Double |
INH |
— |
05 |
— |
1 |
3 |
|
LSR |
Logical Shift Right |
EXT |
— |
74 |
hh ll |
3 |
6 |
|
IND, X |
— |
64 |
ff |
2 |
6 |
|||
IND, Y |
18 |
64 |
ff |
3 |
7 |
|||
LSRA |
Logical Shift Right A |
INH |
— |
44 |
— |
1 |
2 |
|
LSRB |
Logical Shift Right B |
INH |
— |
54 |
— |
1 |
2 |
|
LSRD |
Logical Shift Right Double |
INH |
— |
04 |
— |
1 |
3 |
|
MUL |
Multiply 8 by 8 |
INH |
— |
3D |
— |
1 |
10 |
|
NEG |
2's Complement Memory Byte |
EXT |
— |
70 |
hh ll |
3 |
6 |
|
IND, X |
— |
60 |
ff |
2 |
6 |
|||
IND, Y |
18 |
60 |
ff |
3 |
7 |
|||
NEGA |
2's Complement A |
INH |
— |
40 |
— |
1 |
2 |
|
NEGB |
2's Complement B |
INH |
— |
50 |
— |
1 |
2 |
|
NOP |
No Operation |
INH |
— |
01 |
— |
1 |
2 |
|
ORAA |
OR Accumulator A (Inclusive) |
IMM |
— |
8A |
ii |
2 |
2 |
|
DIR |
— |
9A |
dd |
2 |
3 |
|||
EXT |
— |
BA |
hh ll |
3 |
4 |
|||
IND, X |
— |
AA |
ff |
2 |
4 |
|||
IND, Y |
18 |
AA |
ff |
3 |
5 |
|||
ORAB |
OR Accumulator B (Inclusive) |
IMM |
— |
CA |
ii |
2 |
2 |
|
DIR |
— |
DA |
dd |
2 |
3 |
|||
EXT |
— |
FA |
hh ll |
3 |
4 |
|||
IND, X |
— |
EA |
ff |
2 |
4 |
|||
IND, Y |
18 |
EA |
ff |
3 |
5 |
|||
PSHA |
Push A onto Stack |
INH |
— |
36 |
— |
1 |
3 |
|
PSHB |
Push B onto Stack |
INH |
— |
37 |
— |
1 |
3 |
|
PSHX |
Push X onto Stack |
INH |
— |
3C |
— |
1 |
4 |
|
PSHY |
Push Y onto Stack |
INH |
18 |
3C |
— |
2 |
5 |
|
PULA |
Pull A from Stack |
INH |
— |
32 |
— |
1 |
4 |
|
PULB |
Pull B from Stack |
INH |
— |
33 |
— |
1 |
4 |
|
PULX |
Pull X from Stack |
INH |
— |
38 |
— |
1 |
5 |
|
PULY |
Pull Y from Stack |
INH |
18 |
38 |
— |
2 |
6 |
|
ROL |
Rotate Left |
EXT |
— |
79 |
hh ll |
3 |
6 |
|
IND, X |
— |
69 |
ff |
2 |
6 |
|||
IND, Y |
18 |
69 |
ff |
3 |
7 |
|||
ROLA |
Rotate Left A |
INH |
— |
49 |
— |
1 |
2 |
|
ROLB |
Rotate Left B |
INH |
— |
59 |
— |
1 |
2 |
|
ROR |
Rotate Right |
EXT |
— |
76 |
hh ll |
3 |
6 |
|
IND, X |
— |
66 |
ff |
2 |
6 |
|||
IND, Y |
18 |
66 |
ff |
3 |
7 |
|||
RORA |
Rotate Right A |
INH |
— |
46 |
— |
1 |
2 |
|
RORB |
Rotate Right B |
INH |
— |
56 |
— |
1 |
2 |
|
RTI |
Return from Interrupt |
INH |
— |
3B |
— |
1 |
12 |
|
RTS |
Return from Subroutine |
INH |
— |
39 |
— |
1 |
5 |
|
Mnemonic |
Operation |
Addressing
|
Instruction |
Bytes |
Cycles |
Condition Codes |
||
Prebyte |
Opcode |
Operand |
|
|||||
SBA |
Subtract B from A |
INH |
— |
10 |
— |
1 |
2 |
|
SBCA |
Subtract with Carry from A |
IMM |
— |
82 |
ii |
2 |
2 |
|
DIR |
— |
92 |
dd |
2 |
3 |
|||
EXT |
— |
B2 |
hh ll |
3 |
4 |
|||
IND, X |
— |
A2 |
ff |
2 |
4 |
|||
IND, Y |
18 |
A2 |
ff |
3 |
5 |
|||
SBCB |
Subtract with Carry from B |
IMM |
— |
C2 |
ii |
2 |
2 |
|
DIR |
— |
D2 |
dd |
2 |
3 |
|||
EXT |
— |
F2 |
hh ll |
3 |
4 |
|||
IND, X |
— |
E2 |
ff |
2 |
4 |
|||
IND, Y |
18 |
E2 |
ff |
3 |
5 |
|||
SEC |
Set Carry |
INH |
— |
0D |
— |
1 |
2 |
|
SEI |
Set Interrupt Mask |
INH |
— |
0F |
— |
1 |
2 |
|
SEV |
Set Overflow Flag |
INH |
— |
0B |
— |
1 |
2 |
|
STAA |
Store Accumulator A |
DIR |
— |
97 |
dd |
2 |
3 |
|
EXT |
— |
B7 |
hh ll |
3 |
4 |
|||
IND, X |
— |
A7 |
ff |
2 |
4 |
|||
IND, Y |
18 |
A7 |
ff |
3 |
5 |
|||
STAB |
Store Accumulator B |
DIR |
— |
D7 |
dd |
2 |
3 |
|
EXT |
— |
F7 |
hh ll |
3 |
4 |
|||
IND, X |
— |
E7 |
ff |
2 |
4 |
|||
IND, Y |
18 |
E7 |
ff |
3 |
5 |
|||
STD |
Store Accumulator D |
DIR |
— |
DD |
dd |
2 |
4 |
|
EXT |
— |
FD |
hh ll |
3 |
5 |
|||
IND, X |
— |
ED |
ff |
2 |
5 |
|||
IND, Y |
18 |
ED |
ff |
3 |
6 |
|||
STOP |
Stop Internal Clocks |
INH |
— |
CF |
— |
1 |
2 |
|
STS |
Store Stack Pointer |
DIR |
— |
9F |
dd |
2 |
4 |
|
EXT |
— |
BF |
hh ll |
3 |
5 |
|||
IND, X |
— |
AF |
ff |
2 |
5 |
|||
IND, Y |
18 |
AF |
ff |
3 |
6 |
|||
STX |
Store Index Register X |
DIR |
— |
DF |
dd |
2 |
4 |
|
EXT |
— |
FF |
hh ll |
3 |
5 |
|||
IND, X |
— |
EF |
ff |
2 |
5 |
|||
IND, Y |
CD |
EF |
ff |
3 |
6 |
|||
STY |
Store Index Register Y |
DIR |
18 |
DF |
dd |
3 |
5 |
|
EXT |
18 |
FF |
hh ll |
4 |
6 |
|||
IND, X |
1A |
EF |
ff |
3 |
6 |
|||
IND, Y |
18 |
EF |
ff |
3 |
6 |
|||
SUBA |
Subtract Memory from A |
IMM |
— |
80 |
ii |
2 |
2 |
|
DIR |
— |
90 |
dd |
2 |
3 |
|||
EXT |
— |
B0 |
hh ll |
3 |
4 |
|||
IND, X |
— |
A0 |
ff |
2 |
4 |
|||
IND, Y |
18 |
A0 |
ff |
3 |
5 |
|||
SUBB |
Subtract Memory from B |
IMM |
— |
C0 |
ii |
2 |
2 |
|
DIR |
— |
D0 |
dd |
2 |
3 |
|||
EXT |
— |
F0 |
hh ll |
3 |
4 |
|||
IND, X |
— |
E0 |
ff |
2 |
4 |
|||
IND, Y |
18 |
E0 |
ff |
3 |
5 |
|||
SUBD |
Subtract Memory from D |
IMM |
— |
83 |
jj kk |
3 |
4 |
|
DIR |
— |
93 |
dd |
2 |
5 |
|||
EXT |
— |
B3 |
hh ll |
3 |
6 |
|||
IND, X |
— |
A3 |
ff |
2 |
6 |
|||
IND, Y |
18 |
A3 |
ff |
3 |
7 |
|||
SWI |
Software Interrupt |
INH |
— |
3F |
— |
1 |
14 |
|
TAB |
Transfer A to B |
INH |
— |
16 |
— |
1 |
2 |
|
TAP |
Transfer A to CC Register |
INH |
— |
06 |
— |
1 |
2 |
|
TBA |
Transfer B to A |
INH |
— |
17 |
— |
1 |
2 |
|
TEST |
TEST (Only in Test Modes) |
INH |
— |
00 |
— |
1 |
* |
|
TPA |
Transfer CC Register to A |
INH |
— |
07 |
— |
1 |
2 |
|
TST |
Test for Zero or Minus |
EXT |
— |
7D |
hh ll |
3 |
6 |
|
IND, X |
— |
6D |
ff |
2 |
6 |
|||
IND, Y |
18 |
6D |
ff |
3 |
7 |
|||
TSTA |
Test A for Zero or Minus |
INH |
— |
4D |
— |
1 |
2 |
|
TSTB |
Test B for Zero or Minus |
INH |
— |
5D |
— |
1 |
2 |
|
TSX |
Transfer Stack Pointer to X |
INH |
— |
30 |
— |
1 |
3 |
|
TSY |
Transfer Stack Pointer to Y |
INH |
18 |
30 |
— |
2 |
4 |
|
TXS |
Transfer X to Stack Pointer |
INH |
— |
35 |
— |
1 |
3 |
|
TYS |
Transfer Y to Stack Pointer |
INH |
18 |
35 |
— |
2 |
4 |
|
WAI |
Wait for Interrupt |
INH |
— |
3E |
— |
1 |
** |
|
XGDX |
Exchange D with X |
INH |
— |
8F |
— |
1 |
3 |
|
XGDY |
Exchange D with Y |
INH |
18 |
8F |
— |
2 |
4 |
|
Mnemonic |
Operation |
Addressing
|
Instruction |
Bytes |
Cycles |
Condition Codes |
||
Prebyte |
Opcode |
Operand |
|
Cycle:
* |
Infinity or until reset occurs. |
** |
12 cycles are used beginning with the opcode fetch. A wait state is entered which remains in effect for an integer number of MPU E-clock cycles (n) until an interrupt is recognized. Finally, two additional cycles are used to fetch the appropriate interrupt vector (total = 14 + n). |
Operands:
dd |
= |
8-bit direct address $0000-$00FF. (High byte assumed to be $00.) |
ff |
= |
8-bit positive offset $00 (0) to $FF (255) added to index. |
hh |
= |
High order byte of 16-bit extended address. |
ii |
= |
One byte of immediate data. |
jj |
= |
High order byte of 16-bit immediate data. |
kk |
= |
Low order byte of 16-bit immediate data. |
ll |
= |
Low order byte of 16-bit extended address. |
mm |
= |
8-bit bit mask (set bits to be affected). |
rr |
= |
Signed relative offset $80 (-128) to $7F (+127). Offset relative to the address following the machine code offset byte. |
Condition Codes:
Bit not changed. |
|
Always cleared (logic 0). |
|
Always set (logic 1). |
|
Bit cleared or set depending on operation. |
|
Bit may be cleared, cannot become set. |